Principal Physical Design Engineer
5 days ago
Responsibilities Lead physical implementation at both block and top levels, including floorplanning, placement, clock tree synthesis (CTS), and routing; Drive timing closure, formal verification, low-power analysis, and power optimization; Perform IR drop and electromigration (EM) analysis, as well as physical verification including DRC, LVS, and ESD checks; Support cross-functional integration and validation between frontend and backend design teams; Contribute to the development and refinement of backend flows for advanced process technologies. Requirements Master’s degree or higher in Microelectronics, IC Design, Electrical Engineering, Computer Engineering, or a related field; 10+ years of hands‑on experience in digital backend design for ASIC or SoC products; Proven experience with advanced technology nodes such as 3nm, 4nm, or 6nm, with successful tape‑out records; Strong background working with major foundries such as TSMC or Samsung at either block‑level or full‑chip scale; Proficient with industry‑standard EDA tools, including Cadence and/or Synopsys platforms for P&R, STA, and physical verification; Deep expertise across the full backend flow—from netlist to GDSII—including floorplanning, power planning, placement, optimization, CTS, routing, ECO implementation, RC/SPEF extraction, and STA sign‑off; Solid grasp of static timing analysis and low‑power design techniques (e.g., multi‑VDD, power domains, UPF); Experience with complex SoC projects; familiarity with high‑speed modules such as CPU, DDR, or SerDes is a strong advantage; Proficient in automation and scripting using languages such as Tcl, Perl, or Shell; Strong communication skills and a collaborative mindset, with the ability to work effectively in cross‑functional teams. #J-18808-Ljbffr
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Principal Physical Design Engineer
24 hours ago
Singapore MaxLinear, Inc. Full time $120,000 - $180,000 per yearResponsibilitiesMaxlinear is seeking a Principal Physical Design Engineer (SoC Middle-End - RTL2NETLIST) to join our team in Singapore. Be part of a SoC LPS team dealing with complex Communication ICs (wifi, router, ethernet ) in 7nm and below and focusing on:Perform Design synthesis with Synopsys/Cadence toolset, with full knowledge and understanding of...
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Principal Physical Design Engineer
23 hours ago
Singapore MaxLinear Inc. Full time $180,000 - $250,000 per yearResponsibilities:Maxlinear is seeking a Principal Physical Design Engineer (SoC Middle-End - RTL2NETLIST) to join our team in Singapore. Be part of a SoC LPS team dealing with complex Communication ICs (wifi, router, ethernet ) in 7nm and below and focusing on:Perform Design synthesis with Synopsys/Cadence toolset, with full knowledge and understanding of...
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Principal Physical Design Engineer
2 weeks ago
Singapore MAXLINEAR ASIA SINGAPORE PRIVATE LIMITED Full timeJob Responsibilities Perform Design synthesis with Synopsys/Cadence toolset, with full knowledge and understanding of functional constraints Create timing constraints for functional, DFT modes for synthesis/STA by working closely with Design and DFT Engineers STA/timing closure Write Low power intent file (CPF/UPF) from specification and verifying...
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Principal Physical Design Engineer
12 hours ago
Singapore MAXLINEAR ASIA SINGAPORE PRIVATE LIMITED Full timeJob Responsibilities:- Perform Design synthesis with Synopsys/Cadence toolset, with full knowledge and understanding of functional constraints Create timing constraints for functional, DFT modes for synthesis/STA by working closely with Design and DFT Engineers STA/timing closure Write Low power intent file (CPF/UPF) from specification and verifying...
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Principal Physical AI Engineer
24 hours ago
Singapore ST Engineering Full time $120,000 - $180,000 per yearJob ID: 20269Location:Elect – 100 Jurong East Street, SGDescription:About the RoleWe are looking for a Principal Physical AI Engineer with strong foundations in Multi-Robot System (MRS) and Physical AI to help build next-generation MRS/Swarm collaboration solutions. You will work on real-time distributed/decentralised robotic planning, coordination,...
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Principal Memory Circuit Design Engineer
1 week ago
Singapore Broadcom Full timeFoundation IP Principal Memory Circuit Design Engineer We are looking for energetic and passionate design engineers to join our Central Engineering Group and be part of an elite team responsible for the development of foundation IP for AI products including memory compilers, logic cells and custom macros of all types on the bleeding edge of process...
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Principal Memory Circuit Design Engineer
5 days ago
Singapore Broadcom Full timeOverview Foundation IP Principal Memory Circuit Design Engineer We are looking for energetic and passionate design engineers to join our Central Engineering Group and be part of an elite team responsible for the development of foundation IP for AI products including memory compilers, logic cells and custom macros of all types on the bleeding edge of process...
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Physic Design Engineer
12 hours ago
Singapore BITMAIN DEVELOPMENT PTE. LTD. Full timeJob Description: Responsible for analog/hybrid circuit program planning and design implementation, performance optimization, simulation verification and testing related work; Responsible for the design of high-performance, ultra-low voltage customized circuits under advanced technology. Targeting specific PPA requirements, able to select transistors, layout...
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Principal PCB Design Engineer
2 weeks ago
Singapore FormFactor Inc. Full timeOverview Principal PCB Design Engineer at FormFactor Inc. Responsibilities Primary role to work on automations using Cadence SKILLs to improve MLO/MLC design process. Collaborate on projects internally or with other departments to improve the cycle from design to manufacturing. Work with EDA vendors on new tools or features evaluation. Design engineering for...
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Senior Principal SOC Design Engineer
5 days ago
Singapore Maxlinear (Singapore) Pte. Ltd Full timeSenior Principal SOC Design Engineer Posted today Job Description MaxLinear is seeking a Senior Principal SOC Design Engineer to join our VLSI group. You will be responsible for pre‑silicon RTL coding of blocks, subsystems, and top‑level SOC integration. With deep understanding of design architecture and meticulous attention to detail, you will develop...