Mechanical Design Engineer

6 days ago


Singapore The Supreme HR Advisory Full time

Location: Admiralty Street Working Days: 5 Day A Week Working hours: 9:00am - 6:00pm Salary: $6000 - $8000 (depends experience)Role Overview We are seeking a Mechanical Design Engineer with expertise in designing die ejection modules for semiconductor packaging equipment. The candidate should have hands‐on experience in ejecting ultra‐thin dies (down to 25 μm) from wafers and familiarity with Chip‐on‐Wafer (CoW) package handling for CoWoS assembly. This role demands a deep understanding of stress, warpage, and material behavior during the ejection process to achieve high yield and prevent die damage. Key Responsibilities Lead the design of die ejection modules capable of handling ultra‐thin dies (≤ 25 μm). Develop mechanical tooling and systems to minimize stress, die cracking, or chipping during ejection. Incorporate simulation‐based validation (FEA) for warpage, stress, and deformation analysis. Design ejection solutions that effectively mitigate residue‐related yield loss from wafer dicing tape. Collaborate with motion, control, and vacuum subsystems to ensure synchronized ejection and pick‐up. Work closely with process engineers to optimize ejection force, tape adhesion parameters, and throughput. Design ejector modules for large and warped CoW packages used in CoWoS and 2.5D packaging applications. Develop robust tooling concepts to manage thermal and mechanical stress during CoW ejection. Analyze yield loss due to ejection‐related defects and implement design or process improvements. Support cross‐functional teams in root‐cause analysis and failure prevention. Requirements Bachelor's or Master's degree in Mechanical Engineering, Mechatronics, or related field. 5+ years of experience in semiconductor equipment design, preferably in die handling or ejection systems. Strong background in mechanical stress analysis, warpage modeling, and precision tooling design. Proficiency with SolidWorks, Creo, or equivalent 3D CAD software. Experience with FEA tools (ANSYS, COMSOL, etc.) for stress and deformation analysis. Familiarity with cleanroom design requirements, vacuum systems, and precision motion stages. Prior involvement in CoWoS, 2.5D, or HBM packaging processes. Hands‐on experience with tape residue management, die pick‐up optimization, or die attach automation. Knowledge of wafer dicing, plasma cleaning, and surface preparation techniques. Experience collaborating with process, electrical, and software teams in semiconductor tool development. #J-18808-Ljbffr



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