Senior Silicon Design Engineer
4 weeks ago
THE PERSON:
The ideal candidate should have a deep understanding of analog design and be able to lead, attend, and present at design review meetings with teams worldwide.
KEY RESPONSIBILITIES:
Circuit design of wireline transceiver building blocks (PLL, clock distribution, receiver front-end, transmitter front-end, serializer, deserializer, etc.)
Conduct peer reviews of circuit design and verification results
Work with the validation team to evaluate silicon results
PREFERRED EXPERIENCE:
Extensive experience with high-speed analog design with blocks like ADC, PLL, clock distribution, receiver front-end, transmitter front-end, serializer, deserializer.
Experience with the latest process technologies like 7nm or below FinFET technology.
ACADEMIC CREDENTIALS:
Bachelor's/Master's/PhD Degree in Electronic Engineering
LOCATION:
Singapore
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