Design Verification Engineer

**Location** Singapore, Central Singapore **Job Type** Full Time **Salary** $5,000 - $9,000 Per Month **Date Posted** 1 hour ago Additional Details **Job ID** 5273 **Job Views** 1 **Job Description**: Roles & Responsibilities - Experience in UVM verification methodology - Experience in developing and deploying state-of-the-art verification...

Design Verification Engineer Our client is a young and ambitious SoC design house who dedicated to wireless area. To expand their R&D team and explore overseas market, they are now looking for various design talents in Singapore. **Responsibilities**: - You will responsible for verification platform setup, compile and certificate automated scripts,...

Location: - Singapore- Job Type: - Permanent- Salary: - S$6000 - S$8000 per month- Reference: - BBBH10707_1670230849- Contact: - Catherine Qu- Design Verification Engineer Our client is a young and ambitious SoC design house who dedicated to wireless area. To expand their R&D team and explore overseas market, they are now looking for various design talents...

**Company Overview**: Ambiq has been on a singular mission since 2010 to put intelligence everywhere by creating the most energy-efficient semiconductor solutions for IoT endpoint devices. Using the revolutionary Subthreshold Power Optimized Technology (SPOT®) Platform, Ambiq's record-breaking ultra-low power solutions, including MCU and SoCs, have helped...

One of our US Global Semiconductor IC design is growing their design teams in Singapore. Role : Design Verification Engineer (DV) Location : Singapore Experience : 3 to 7 years. - **Technical Requirements**: - Expert-level UVM and SystemVerilog verification - Advanced coverage-driven verification methodologies - Experience with complex SoC verification...

As a Design Verification Manager, you are expected to carry out the following responsibilities. Be in-charge of a passionate verification team that is constantly pushing the limits Developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode...

As a Design Verification Manager, you are expected to carry out the following responsibilities. Be in-charge of a passionate verification team that is constantly pushing the limits Developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode...

Job Title (Sr./Staff) Design Verification Engineer at OMNIVISION Description As a design verification engineer, you will be part of a passionate verification team that develops and deploys state-of-the-art verification methodologies for complex designs. Your goal is to achieve zero-defect verification using advanced techniques such as UVM, C/C++...

Description: As a design verification engineer, you would be part of a passionate verification team that is constantly pushing the limits – developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification. The goal is...

**The Opportunity** - Will be working as a member of a cross geographic pre-silicon verification team to verify a next generation FPGA SoC. - Will be working with design, architecture team to verify micro-architecture and design across multiple platforms - Job responsibilities will include plan development, test bench implementation, test case creation and...