Senior Digital Systems Architect

2 weeks ago

Singapore beBeeDesign Full time $90,000 - $120,000
Job Title

A distinguished professional is required to spearhead the implementation of ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis). The successful candidate will define ISP HW Architecture based on product features and performance requirements, including gate count and power estimation.

Responsibilities
  • Implement ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis)
  • Define ISP HW Architecture based on product features and performance requirements, including gate count and power estimation
  • Verify Logic at ISP level and Digital System level
  • Optimize Design for less gate count and low power consumption
  • Drive ISP Design activities in close collaboration with ISP Algorithm Team, ISP Design leaders in other sites, and Digital System Design Team
  • Lead, supervise and mentor a team of RTL design engineers
Requirements

To be considered for this challenging role, applicants must possess the following qualifications:

  • Minimum MSEE, or BSEE, or equivalent, plus 7+ years of Digital Design and verification related experience
  • 3+ years project management / people management experience / skill
  • Experience/knowledge in CMOS Image Sensor and image signal processing (ISP)
  • Experience/knowledge in System C/C++, System Verilog, and Catapult HLS tool
  • Ability to lead teams and collaborate effectively with people in different functions
  • Strong time management skills to ensure timely completion of deliverables
  • Good communication and interpersonal skills
  • Results-oriented and adaptable to changes

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