
Expert Low-Latency System Architect
7 days ago
Job Overview: Implement low-latency market data ingestion and order matching systems with nanosecond-level latency requirements.
- Key Responsibilities:
- Data Ingestion: Design, implement, and deploy high-performance market data ingestion systems that meet stringent latency requirements.
- Order Matching: Develop highly scalable and efficient order matching algorithms to minimize latency and ensure accuracy.
- Performance Analysis: Conduct in-depth performance modeling and analysis across various modules of the trading system (data path, memory access patterns, cache hit rate, context switch overhead) to drive system metrics visualization.
- Tuning: Optimize user-space network protocol stacks based on DPDK, leveraging kernel bypass technologies for improved performance.
Requirements:
- Technical Skills:
- Proficient in modern C++ (C++17/20) with strong system-level high-performance programming skills (cache-friendly data structure design, zero-copy data pipelines, CPU affinity binding).
- Solid understanding of CPU architecture (x86_64), cache hierarchy, branch prediction, pipeline stalls, and other hardware-level behaviors.
- In-depth experience in at least one of the following areas:
- Analysis and optimization of core Linux kernel components (network stack, scheduler, memory subsystem).
- CPU microarchitecture analysis using tools like perf, Intel VTune, or Top-Down analysis method.
- SIMD vectorization (AVX2/AVX512) or custom assembly-level optimization.
- Development of system-level latency profiling or microbenchmark toolchains.
- Business Acumen:
- Deep understanding of the WebSocket protocol with ability to implement custom frame parsing and construction.
- Familiarity with I/O multiplexing mechanisms (epoll, io_uring).
- Experience building high-performance WebSocket or FIX/SBE protocol clients.
- Experience with user-space network stack technology (netmap, DPDK).
- Familiar with tick data processing workflows in high-frequency trading environments (market data reconstruction, reordering mechanisms).
- Knowledge of PTP/TSC synchronization and system clock stability tuning.
Bonus Points:
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