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Expert Digital Fault Architect

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Singapore beBeeDigitalFaultTolerance Full time $80,000 - $120,000

Digital Fault Tolerance Expert

We are seeking an exceptional Digital Fault Tolerance Specialist to drive the development and implementation of complex digital fault architectures. As a critical member of our organization, you will be responsible for collaborating closely with design teams to ensure seamless integration of digital fault structures into our products.

Responsibilities:

  • Closely collaborate with design teams to integrate digital fault structures into our products, ensuring optimal performance and reliability.
  • Develop, implement, and verify digital fault schemes on hard-IPs in FPGAs, driving innovation and excellence in digital fault tolerance.
  • Pursue the development and implementation of cutting-edge techniques for testing digital logic using scan compression, stuck-at, transition, and path-delay fault models.
  • Resolve complex scan/MBIST pattern issues on bench/ATE, identifying root causes and implementing corrective actions to drive continuous improvement.
  • Support diagnosis and yield enhancement initiatives throughout the product lifecycle, fostering a culture of excellence and collaboration.

Requirements:

  • Bachelor's or Master's degree in Electrical/Electronic/Computer Engineering with a minimum of 3 years of experience in digital fault tolerance.
  • Expertise in creating and implementing complex chip-level digital fault architectures, driving innovation and excellence in digital fault tolerance.
  • Familiarity with DFT implementation, including scan and scan compression at IP and SoC levels, ensuring seamless integration and optimal performance.
  • Proficiency in DFT tools, ATPG (stuck-at, at-speed, path-delay), and scan compression, driving efficiency and effectiveness in digital fault tolerance.
  • Strong knowledge of logic design using Verilog, synthesis, and static timing analysis (STA), ensuring accurate and reliable digital fault architectures.
  • Experience in developing test benches and simulations in RTL/Gate/SDF environments, driving innovation and excellence in digital fault tolerance.
  • Familiarity with MBIST is advantageous, but not required.
  • Knowledge of FPGA synthesis and design flow is beneficial, but not necessary.
  • Experience with post-silicon debug and bench setup is desirable, but not required.
  • Comfortable working in Linux environments and proficient in scripting languages such as Perl, Tcl, Python, etc., driving efficiency and effectiveness in digital fault tolerance.
  • Excellent communication skills, self-motivation, and ability to thrive in a global team environment, fostering a culture of excellence and collaboration.

What We Offer:

A dynamic work environment that fosters growth and collaboration, paired with opportunities to develop your expertise and contribute to cutting-edge projects, driving innovation and excellence in digital fault tolerance.