Physical Design Engineer x 5
2 weeks ago
As a Physical Design Engineer at BITSILICA PTE. LTD., you will be responsible for designing and developing high-performance and low-power digital ICs. Your expertise in netlist to GDSII conversion, hierarchical partitioning, and budgeting of block-level subsystems will be invaluable to our team.
Key Responsibilities:
• Netlist to GDSII at block level, subsystem level, and full chip
• Implementation of high-performance (HP) cores and low-power designs
• Timing signoff in loop through STA and ECO cycle at block and interface
• Block-level floor planning, power planning, and IR drop analysis
• Scan chain reordering, scan chain repartitioning, and CTS expertise
Required Skills:
• PnR tools such as Synopsys ICC/ICC2 and/or Cadence Innovus
• Perl, Static Timing Analysis, Timing Closure, Floorplanning, TCL, Scripting, IP, FPGA, TCLTK, SoC, Python, Cadence, ASIC, Electronic Design Automation (EDA), Debugging, Physical Design, VLSI
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