Hardware Engineer Position

6 days ago

Singapore NTU (Nanyang Technology University- Main Office-HR) Full time
NTU

Built on a culture of excellence, the School of Electrical and Electronic Engineering is renowned for its high academic standards and research. With over 3,000 undergraduates students and 1,000 graduate students it is one of the largest EEE schools in the world and ranks 10th in the field of Electrical & Electronic Engineering in the QS World University Rankings by Subjects.

The School has become one of the world's largest engineering schools that nurtures competent engineers and researchers. Each year, the School graduates over a thousand students who are ready to take on great ambitions and challenges.

We are seeking a highly skilled Research Associate with experience in RISC-V architecture. The successful candidate will be responsible for integrating a Hardware AES and ASCON Accelerator into the RISC-V CVA6 core. This role requires deep knowledge of hardware design, cryptographic algorithms, and the RISC-V instruction set architecture (ISA).

Job Objectives:
  • To integrate a Hardware AES Accelerator and ASCON Lightweight Cryptography Accelerator into the RISC-V CVA6 (Ariane) core.
  • To implement memory-mapped interfaces or custom instructions for the accelerators to interface with the CVA6 core.
  • To collaborate on the integration of the accelerators into the core's execution pipeline.
Cryptography Expertise:
  • To define and implement custom RISC-V instructions to utilize the AES and ASCON hardware accelerators, if needed.
  • To modify the RISC-V CVA6 decode and execution stages to handle the new cryptographic instructions.
  • To work out the toolchain to ensure assembler, compiler, and simulation support for the custom instructions.
Methodology:
  • To conduct simulations to evaluate the performance, latency, and throughput of the accelerators within the CVA6 pipeline.
  • To work closely with the AES and ASCON accelerator design team to ensure proper testing and debugging of the hardware integration.
Requirements:
  • Masters degree in Electrical Engineering, Computer Engineering, or a related field.
  • Proven experience with RISC-V architecture, especially with custom instruction extensions and pipeline modifications.
  • Proficiency in HDL languages (Verilog, VHDL, or SystemVerilog) and RTL design.
  • Proficiency in toolchain modification, including the ability to extend assemblers and compilers (GCC, LLVM) for custom hardware instructions.
  • Proficiency of FPGA development tools such as Vivado, Quartus, or similar for prototyping.
Prioritized Skills:
  • Strong understanding of ASIC/FPGA design flows, including synthesis, place and route, and timing closure.
  • Experience in cryptography and implementing cryptographic algorithms in hardware (AES, ASCON, etc.).

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