
Vice President of Physical Chip Design
6 days ago
We are seeking a highly skilled and experienced Senior Physical Chip Design Engineer to lead the development and optimization of low-power, high-performance chip design processes. Our ideal candidate will possess a strong technical background in physical design, including floor planning, placement and routing, power distribution network architecture, and timing closure.
Key Responsibilities:
- Lead full-chip floor planning and place-and-route management to ensure optimal performance, power, and area utilization.
- Architect and optimize power distribution networks to maintain power integrity and minimize losses, conducting thorough power grid analysis.
- Drive timing closure efforts, collaborating with cross-functional teams to meet challenging performance targets.
- Take ownership of power integrity and signal integrity signoff, performing necessary analysis and optimizations.
- Lead comprehensive design rule checks (DRC) and layout versus schematic (LVS) verifications to ensure design compliance and correctness.
Required Skills and Qualifications:
- Extensive experience in physical chip design using industry-standard tools such as Synopsys IC Compiler, Cadence Innovus, or equivalent.
- Strong scripting and programming skills (Perl, TCL, Python, C++) to automate tasks and improve design efficiency.
- Excellent communication and teamwork skills, with ability to mentor and provide technical guidance to junior engineers.
Benefits:
This is an exciting opportunity for an experienced physical chip design engineer to join our team and contribute to the development of innovative, high-performance chip designs.
Note:
The successful candidate will have the opportunity to work on a variety of challenging projects, collaborate with cross-functional teams, and develop their technical skills and expertise.
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