Physical Chip Design Engineer
1 week ago
Overview We are looking for a highly skilled Physical Chip Design Engineer to lead the development of low-power and high-performance chip design processes . This is a critical role that requires deep expertise in advanced semiconductor technologies and the ability to drive full-chip physical design workflows from start to finish. Responsibilities Low-Power Physical Design Workflows: Lead and optimize processes to enhance energy efficiency while maintaining chip performance. Full-Chip Floor Planning & Place-and-Route: Oversee floor planning to ensure optimal performance, power, and area. Manage place-and-route processes for efficient, functional designs. Power Network Design & Analysis: Design and optimize power distribution networks, perform grid analysis to ensure power integrity and low-power design. Timing Closure, Power Integrity, & Signal Integrity: Resolve timing challenges, ensure power and signal integrity signoff, and perform necessary optimizations. Physical Verification (DRC & LVS): Conduct thorough physical verification, including Design Rule Checks (DRC) and Layout Versus Schematic (LVS) to ensure compliance with design specifications. Qualifications Education: Bachelor’s degree or higher in Electronics , Electrical Engineering , Computer Science , or related field. Advanced degrees (Master’s/Ph.D.) are a plus. Experience: 4-5 years of hands-on experience in physical design , with expertise in low-power, high-performance chip design . Experience with 12nm and below semiconductor technologies and tape-out processes is essential. Technical Skills: Expertise in full-chip floor planning , place-and-route methodologies , and physical verification (including DRC and LVS ). In-depth knowledge of power network design , IR drop analysis , and timing closure . Proficiency in Synopsys IC Compiler , Cadence Innovus , or similar tools. Proficiency with Static Timing Analysis (STA) tools. Programming Skills: Strong scripting skills in Perl , TCL , Python , and C++ . #J-18808-Ljbffr
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Physic Design Engineer
7 hours ago
Singapore BITMAIN DEVELOPMENT PTE. LTD. Full timeJob Description: Responsible for analog/hybrid circuit program planning and design implementation, performance optimization, simulation verification and testing related work; Responsible for the design of high-performance, ultra-low voltage customized circuits under advanced technology. Targeting specific PPA requirements, able to select transistors, layout...
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Physical Design Engineer
1 week ago
Singapore ALPSOFT TECHNOLOGIES PTE. LTD. Full time**Responsibilities**: - Full responsible for Netlist-to-GDS physical design implementation of 12nm/6nm/4nm and below advanced process chips. - Block owner, take block of 2~3 Million instances, working on Synthesis/APR(auto place and route)/Signoff - Block coordinator role for more than 5~10 blocks, solving the critical issue and give the solution to block...
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Physical Design Engineer
5 days ago
Singapore ByteDance Full time**Physical Design Engineer - Singapore** - Singapore Regular - R&D - Hardware Job ID: A30541 **Responsibilities** Team Introduction The Silicon Platform Team acts as the core R&D middleware group for chip development within the company. The team covers the full spectrum of the chip design flow, including Logic Synthesis, Design for Testability (DFT),...
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Physical Design Engineer
1 week ago
Singapore ByteDance Full timeResponsibilities The Silicon Platform Team acts as the core R&D middleware group for chip development within the company. The team covers the full spectrum of the chip design flow, including Logic Synthesis, Design for Testability (DFT), Backend Design, Physical and STA (Static Timing Analysis) Signoff, as well as Power Integrity, IR drop, and...
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Physical Design Engineer
5 days ago
Singapore Bitmain Development Pte Ltd Full timeResponsibilities Responsible for digital circuit physical implementation (RTL to GDS) and PV/PI signoff; perform full-chip STA signoff, participate in defining STA signoff standards, and conduct SPICE simulation for critical timing paths; Develop, optimize, and maintain PR/PV/PI/STA design flows; support the introduction of advanced technology nodes and EDA...
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Singapore LEADTOP TECHNOLOGY PTE. LTD. Full timeWe are a chip design company invested by an international consortium and founded by a senior chip design technical team. The company is headquartered in Singapore and will take root in Singapore for long-term development. The company has strong R&D capabilities and its core technical team members all have more than 10 years of experience in chip design. We...
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Singapore LEADTOP TECHNOLOGY PTE. LTD. Full timeWe are a chip design company invested by an international consortium and founded by a senior chip design technical team.The company is headquartered in Singapore and will take root in Singapore for long-term development.The company has strong R&D capabilities and its core technical team members all have more than 10 years of experience in chip design.We have...
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Physical Design Engineer
2 weeks ago
Singapore BITSILICA PTE. LTD. Full time**Physical Design Engineer** Experience : 3+ Years Salary Range :SGD 7000-10000 **Skills & Technical Expertise Required**: Netlist to GDSII at block level, Subsystem Level and at Full chip. Worked on multiple tapeouts on Netlist to GDSII Hierarchical partitioning and budgeting of block-level subsystems. Implementation of high performance (HP) cores,...
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Singapore STAFFKING PTE. LTD. Full time**Job Highlights**: Competitive salary Career growth opportunities Work with advanced technologies Collaborative team environment - Collaborate with the design team to develop chip floorplans, clock structures, and power plans. - Perform physical design tasks from Netlist to GDSII, including placement and routing (P&R), formal verification, and static timing...
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Physical Design Engineer
2 days ago
Singapore Voice Way Full time $180,000 - $250,000 per yearJob Description:Lead physical implementation at both block and top levels, including floorplanning, placement, clock tree synthesis (CTS), and routing;Drive timing closure, formal verification, low-power analysis, and power optimization;Perform IR drop and electromigration (EM) analysis, as well as physical verification including DRC, LVS, and ESD...