High-Speed Serdes Architect
3 weeks ago
At JDA WMS PTE. LTD., we're seeking a highly skilled High-Speed Serdes Architect to join our team. As a key member of our IP design group, you will be responsible for architecting and planning competitive analysis and roadmaps for 112G LR Serdes PHY IP, as well as formulating specifications. Your expertise in designing and implementing PHY IP architecture for 112G LR Serdes will be crucial in developing in-house 112G LR Serdes PHY IP, ensuring the achievement of PPA (Power, Performance, Area) indicators.
Key Responsibilities
- Architect and plan competitive analysis and roadmap for 112G LR Serdes PHY IP, and formulate specifications.
- Design and implement PHY IP architecture for 112G LR Serdes.
- Develop in-house 112G LR Serdes PHY IP, ensuring achievement of PPA (Power, Performance, Area) indicators.
- Collaborate with the back-end team to complete physical implementation of PHY IP and achieve timing closure.
- Design and implement test chips, package design, test board design, and oversee post-silicon bring-up and testing.
Requirements
- Over 10 years of experience in Serdes PHY IP design with successful tape-outs.
- More than 5 years of experience specifically in Serdes PHY IP architecture design.
- Successful development experience in advanced technologies for 112G LR Serdes or higher.
- Deep familiarity with the Serdes and high-speed interface PHY IP market, competitive landscape, and extensive experience in product road mapping and definition.
- Preference for candidates with experience in similar IP design, subsystem development, tape-out, debugging, and successful mass production.
- Strong communication skills, high sense of responsibility, commitment to delivery, and excellent team collaboration skills.
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