Physical Design Engineer
2 weeks ago
Responsibility
- Responsible for high-performance block implementation (RTL to GDSII).
- Perform block level floor planning, power grid implementation, APR placement, timing optimization, CTS and routing.
- Close the design to meet timing, power budget and area targets.
- Run physical verification flows (DRC/LVS/EM/IR), and implement fixes to meet the requirements.
- Implement ECO's to address functional bugs, timing and physical verification violations.
- Responsible for the generation and maintenance of block-level STA constraints and performing STA signoff checks.
- Responsible for timing model generation and supporting the successful integration of blocks into SOC.
Qualification
- At least 3 years of hands-on experience in digital-physical design.
- Bachelor/Master's degree in Electrical Engineering with an emphasis in IC design
- Experience with digital Physical design and Static Timing Analysis
- Experience in floor planning and routing.
- Experience in advanced process nodes (5nm).
- Good experience with Synopsys implementation tools (DC, ICC2), and experience with Cadence (Innovus) implementation tool is a plus.
- Experience in Mentor Verification tool, Calibre.
- Proficient in TCL coding, Perl/Python knowledge is a plus.
- Good written and communication skills.
Static Timing Analysis
Timing Closure
Floorplanning
TCL
Scripting
Routing
Written Communication
Communication Skills
Cadence
Budgeting
IC
Physical Design
Electrical Engineering
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