Senior Physical Design Engineer
2 weeks ago
Our client is a reputable and prominent Singapore based startup firm that focuses on strong research and development capabilities in chip design. Due to massive hiring plans, the firm is looking to build up their backend design engineering team and are looking to hire multiple senior physical design engineers to be part of their young and dynamic engineering team.
Key Responsibilities:
- Physical Design Implementation: Perform block- and chip-level floorplanning, placement, CTS, and routing.
- Timing Closure: Conduct static timing analysis (STA), resolve violations, and optimize performance.
- Power Optimization: Minimize dynamic and leakage power through low-power design techniques such as clock gating and multi-Vt optimization.
- Design-for-Manufacturability (DFM) & Design-for-Testability (DFT): Ensure the design is manufacturable and meets test coverage requirements.
- Physical Verification: Run and debug DRC, LVS, ERC, and other physical signoff checks.
- IR Drop and Reliability Analysis: Perform power integrity, electromigration, and signal integrity analysis.
- EDA Tool Flow & Scripting: Develop and enhance design flows using EDA tools from Synopsys, Cadence, or Mentor Graphics, and automate processes using scripts (TCL, Perl, Python).
- Collaboration: Work with cross-functional teams to align physical design constraints with architectural and functional requirements.
- Technology Node Expertise: Work on advanced process nodes to optimize layouts and meet design constraints.
Requirements & Qualifications:
- Education: Bachelor's in Electronic Engineering, Electrical Engineering, Computer Science, microelectronics or a related field.
- Experience: 5+ years of experience in physical design with digital backend design field. Hands-on project experience is required. Tapeout experience at advanced technology is preferred.
- Scripting Knowledge: Proficiency in scripting languages like TCL, Python, and Perl to automate tasks.
- Experience in full-chip physical design.
- Familiarity with machine learning techniques for physical design optimization.
- Knowledge of system-level power and performance trade-offs.
Perl
Signal Integrity
MASSIVE
Static Timing Analysis
Timing Closure
Floorplanning
Scripting
LVS
Routing
EDA
Reliability
Python
Cadence
Physical Design
Electrical Engineering
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