PMIC Reference HW Design Engineer

Overview">This role involves designing high-performance PMIC reference hardware for various Qualcomm chipsets. The ideal candidate will have a strong understanding of electrical engineering concepts, circuit solving skills, and experience in PCB design and component selection.">Responsibilities">">Design and optimize PMIC reference boards and evaluation kits...

Job DescriptionAt QUALCOMM GLOBAL TRADING PTE. LTD., we are seeking an Electrical Engineer to join our PMIC Systems group as a PMIC Reference HW Design Engineer.Key Responsibilities:Design and optimize PMIC PCB floorplan, schematic, layout, phone thermal solution, and eBOM selection for test platforms and customer reference design and evaluation kits.Develop...

Job OverviewIn a collaborative and dynamic environment at QUALCOMM GLOBAL TRADING PTE. LTD., we are seeking an experienced PMIC Reference HW Design Engineer to join our team. With a strong focus on innovation and excellence, this role offers the opportunity to design and optimize PMIC PCBs for Qualcomm chipset-based phone designs.Responsibilities:As a key...

Company OverviewQualcomm Global Trading PTE. LTD. is a leading technology company that designs and manufactures innovative products for the wireless industry.About the RoleWe are seeking an experienced PMIC Reference HW Design Engineer to join our team. As a member of our design team, you will be responsible for designing and optimizing PMIC PCB floorplans,...

Company:Qualcomm Global Trading Pte. Ltd. Job Area:Interns Group, Interns Group Interim Engineering Intern - HW Qualcomm Overview:Qualcomm is a company of inventors that unlocked 5 G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It...

About the RoleWe are seeking a highly skilled and motivated High Performance ASIC Design Engineer to join our team at Expedera R&D PTE. LTD.Job SummaryThis is an exciting opportunity for a talented individual to develop their skills in designing cutting-edge ASICs that power AI accelerators. The successful candidate will work closely with our HW/SW...

Job OverviewExpedera R&D PTE. LTD. is seeking a skilled Digital IC Design Engineer to join our team in developing cutting-edge AI accelerators. This role involves designing and verifying the hardware microarchitecture, RTL design, and exploring power/performance/area optimization.About the RoleThis is an entry-level position that requires a Bachelor's degree...

Roles & ResponsibilitiesRESPONSIBILITIES INCLUDE, BUT ARE NOT LIMITED TO: Develop HW microarchitecture, RTL design and verification for Expedera AI accelerators (Silicon IP) Explore HW design space power/performance/area optimization Collaborate with HW/SW architects in HW/SW co-design Execute with DevOps for quality assuranceREQUIRED QUALIFICATIONS AND...

Responsibilities:Responsible for implementing ISP Algorithm into HW using Verilog, System Verilog and/or System C (High Level Synthesis)Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation Verify Logic at ISP level and Digital System level Optimize Design for less gate count and low...

Responsibilities: Responsible for implementing ISP Algorithm into HW using Verilog, System Verilog and/or System C (High Level Synthesis) Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation Verify Logic at ISP level and Digital System level Optimize Design for less gate count and low...

Responsibilities: Responsible for implementing ISP Algorithm into HW using Verilog, System Verilog and/or System C (High Level Synthesis)Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation Verify Logic at ISP level and Digital System level Optimize Design for less gate count and low...

Responsibilities: Responsible for implementing ISP Algorithm into HW using Verilog, System Verilog and/or System C (High Level Synthesis) Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation Verify Logic at ISP level and Digital System level Optimize Design for less gate count and low...

Why Patients Need You Whether you are involved in the design and development of manufacturing processes for products or supporting maintenance and reliability, engineering is vital to making sure customers and patients have the medicines they need, when they need them. Working with our innovative engineering team, you'll help bring medicines to the...

We are seeking a skilled Senior RTL Design Engineer to join our team at OMNIVISION TECHNOLOGIES SINGAPORE PTE. LTD.Company OverviewOMNIVISION TECHNOLOGIES SINGAPORE PTE. LTD. is a leading provider of image sensor solutions. Our company is dedicated to delivering high-quality products that meet the needs of our customers.About the JobThis is an exciting...

Roles & ResponsibilitiesResponsibilities Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis) Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation Verify Logic at ISP level and Digital System level Optimize Design for...

What’s the role?Your primary accountabilities as a Process Control Senior Engineer include: Improve robustness of Base Layer control performance, delivery of high uptime and low operator intervention rates. Conduct daily base layer performance monitoring, provide technical support and lead troubleshooting for control and safeguarding related issues....

Responsibilities: Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis)Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation Verify Logic at ISP level and Digital System level Optimize Design for less gate count and low...

Roles & ResponsibilitiesResponsibilities Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis) Verify Logic at ISP level and Digital System level Optimize Design for less gate count and low power consumption Drive ISP Design activities in close collaboration with ISP Algorithm Team ...

Roles & ResponsibilitiesResponsibilities Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis) Verify Logic at ISP level and Digital System level Optimize Design for less gate count and low power consumption Drive ISP Design activities in close collaboration with ISP Algorithm Team ...

Roles & ResponsibilitiesResponsibilities Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis) Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation Verify Logic at ISP level and Digital System level Optimize Design for...