Lead ASIC RTL/SoC Design Engineer for AI In-Memory

3 days ago

Singapur, singapore TETRAMEM INC Full-time

TetraMem is hiring a senior RTL/SoC engineer to drive RTL design, simulation, and verification for ASIC/SoC products. You will collaborate with backend teams, optimize PPA, and mentor junior engineers in a fast-paced startup environment.

The role requires strong Verilog/SystemVerilog expertise, experience with VCS/Verdi, and familiarity with AMBA protocols, ARM cores, and IP integration across complex SoC architectures.