Senior Staff Digital Architect
2 weeks ago
We are Silicon Labs. We are a leader in secure, intelligent wireless technology for a more connected world. Our integrated hardware and software platform, intuitive development tools, unmatched ecosystem and robust support make us the ideal long-term partner in building advanced industrial, commercial, home and life applications. We make it easy for developers to solve complex wireless challenges throughout the product lifecycle and get to market quickly with innovative solutions that transform industries, grow economies and improve lives.
Meet the Team
The Digital Subsystems (DSS) team is responsible for the research and development of digital IP, Subsystem, and IC architectures from concept to production. We develop compute engines, processors, accelerators, peripherals, and system IP. We develop IC architectures for multi-core SoCs with an energy-efficient compute backbone for IoT connectivity, security, and sensing subsystems. We define system solutions along with Marketing, Systems, and Software teams with the Silicon Labs’ AI/ML, RISC-V, Vision, Audio/DSP, Display, Modeling, and Compute workstreams. Our activities include advanced research and development, high-level modeling, architecture, RTL design, timing/power/area optimization, and formal and UVM verification within an automated framework. We value innovation, simplicity, quality, and smart development processes within a highly collaborative and learning-driven team.
Responsibilities
As a technical leader within an advanced digital architecture team, you will be responsible for product definition through requirement gathering, consensus building, analysis, and modeling using your extensive knowledge of system, IC, and IP design. You will work closely with marketing, IC and IP design, modeling, and software teams. IPs include subsystems, accelerators, peripherals, system IP, advanced I/O, and processors. Upon joining Silicon Labs, your experience and resourcefulness will expand our wireless, AI, vision, display, and audio capabilities by optimizing compute, interconnect, and memory systems to produce the industry’s most connected and energy-efficient IoT Wireless MCUs.
Clearly defining architectures by authoring architectural specifications
Exploring and investigating system solutions through hardware/software partitioning
Analyzing usecases and mapping them into a proposed architecture
Analyzing proposed architectures for power, performance, and area trade-offs
Gathering, analyzing, and developing requirements
Communicating and presenting your ideas
Reviewing micro-architectural specifications
Skills You Will Need
Demonstrated experience in building SoC interconnect, smart caches, and memory systems
Demonstrated experience in defining and designing high-complexity designs (accelerators, processors, bus-fabric, DMA, complex I/O peripherals, etc.)
Excellent understanding of embedded systems, their hardware-software partitioning, workloads, and features
Excellent verbal and written communications skills
Good understanding of:
Low power design, architectures, and strategies
Asynchronous design, synchronization techniques, and strategies to minimize latency
Security and isolation in areas such as root-of-trust, secure communication, bus level security, etc.
Hardware powerup and secure software bootstrapping
HDL-based RTL logic design
Front-end design tools, methodologies, and flows
Debug in simulation, FPGA, and silicon environments
Design for Test and Manufacturing
Preferred Experience & Skills (any of the below):
Experience with human-interface devices (microphones, speakers, cameras, displays, etc.)
Experience in design of microprocessors (pipeline, execution units, buses, etc.)
Experience in design of math-centric designs (security primitives, DSP units, AI/ML, etc.)
Scripting skills (BASH, UNIX commands, TCL, Perl, etc.)
Experience in high-level system modeling (Python, C++, SystemC, Renode, etc.)
FPGA emulation
Benefits & Perks:
Employee Stock Purchase Plan (ESPP)
Insurance plans with Outpatient cover
Flexible work policy
#LI-Hybrid
#LI-DK1
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