Senior/Staff ISP RTL Design Engineer
6 months ago
Description
Responsibilities:
Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis) Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation Verify Logic at ISP level and Digital System level Optimize Design for less gate count and low power consumption Drive ISP Design activities in close collaboration with ISP Algorithm TeamRequirements:
Minimum MSEE, or BSEE, or equivalent, plus 3+ years of Digital Design and verification related experience Experience / knowledge in CMOS Image Sensor and image signal processing (ISP) Experience / knowledge in System C/C++, System Verilog, and Catapult HLS tool. Strong debugging and problem-solving skills Good communication and interpersonal skills Result oriented and embrace change behaviours-
Senior ISP RTL Design Manager
4 weeks ago
Singapur, Singapore OMNIVISION Full timeJob SummaryAs a Senior ISP RTL Design Manager at OMNIVISION, you will be responsible for implementing ISP algorithms into hardware using Verilog, SystemVerilog, and/or SystemC. You will define the ISP hardware architecture based on product features and performance requirements, and verify logic at the ISP and digital system levels. Additionally, you will...
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Senior ISP RTL Design Manager
6 months ago
Singapur, Singapore OMNIVISION Full timeDescription Responsibilities: Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis) Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation Verify Logic at ISP level and Digital System level Optimize Design for less...
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Singapur, Singapore OMNIVISION Full timeJob SummaryWe are seeking a highly skilled RTL Design Engineer to join our team at OMNIVISION. As a key member of our ISP Algorithm team, you will be responsible for implementing ISP algorithms into hardware using Verilog, SystemVerilog, and/or SystemC.Responsibilities:Implement ISP algorithms into hardware using Verilog, SystemVerilog, and/or SystemC.Define...
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