[2025 Talent Pipeline] Timing Signoff Engineer

5 hours ago


Singapore 聯發科技 Full time

[What you will do] - Work on timing sign off, convergence, automations and methodology development. - Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus. - Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation. - Evaluate multiple timing methodologies/tools on different designs and technology nodes. - Knowledge in design automation using TCL/Perl/Python - Familiar with process technology enablement: Spice simulation Hspice/FineSim, Monte Carlo. Silicon to spice model correlation. - Knowledge in STA timing analysis basics, AOCV/POCV/LVF concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling
[Are you the right talent?] - Bachelor’s Degree/ Master’s Degree in Electrical/Computer Engineering - Knowledge in ARM/IMG/Tensilica Processor Familiarity, Silicon Debug and/or Functional/Direct Test Verification - Familiar with assertion-based verification (SVA) & System Verilog language - Knowledge in Processor verification, FPGA verification and/or Formal verification - Familiar with Synopsys ICC (preferred) or Cadence or Magma tools from netlists to GDS is a plus - Knowledge in graphics processor implementation/power reduction flows and methodology from RTL to GDS (including synthesis, floor-planning, placement, CTS, routing, timing optimization, physical verification) is a plus - Knowledge of high-speed/low power IP and custom circuit design is a plus - Familiar with power noise and reliability tools such as Redhawk and Voltus - Good communication and scripting skills



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