Standard Cell Library Engineer

2 weeks ago


Singapore 聯發科技 Full time

[What you will do] You will be in a energetic team working on advanced technology development, as the pioneer to setup leading edge design platform for MediaTek multi-vertical projects. - Develop complex circuit block, test key for leading-edge process node (planar, finfet, nanosheet) from schematic netlist to gds. - Develop standard cell library from architecture evaluation, PPA assessment and customized cell design with different PPA purpose and IP blocks. - Work with layout engineer for design implementation and physical verification including DRC/LVS/ERC/ANT. - Perform layout extraction, simulation, analyze simulation data, including performance, power, leakage, for layout dependent effect study. - Work with digital team and testing team for design implementation and chip level silicon data collection. - Develop processing flow for silicon data analysis, visualization, AI model regression. - Develop advanced library generation methodology and flow, including characterization, kit generation, regression, and quality assurance. - Perform timing/power/constraint/noise/LVF variation characterization for standard cell or complex circuit blocks. - Work with circuit designer and tool vendors to tackle modelling difficulties, like accuracy and runtime issues, especially for complex circuit blocks. - Responsible for new kits enablement and evaluation, like EM characterization, aging characterization. - Involve with data analysis and machine learning as well for circuit performance and power assessment. #LI-WC1
[What you bring] - BS/MS in Electrical and Electronic Engineering/Computer Engineering/Computer Science with minimum 3 years(MS) or 5 years(BS) industry experience. (We have entry level position with the same function, no prior experience is required.) - Familiar with Python, Perl, Tcl or C/C++ for flow development and data analysis, machine learning. - Basic knowledge of digital design and/or circuit design. - Solid understanding of foundation IP design, with device physics, transistor level circuit, layout dependent effect knowledge. - Experience of test chip design in FinFet/Nanosheet technologies is a plus, with understanding of DRM, layout rules, PV check, and simulation skills. - Strong communication and teamwork skills to collaborate effectively with cross-functional teams.



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