Spot Low Power Engineer

6 days ago

Singapore HUBBED PTE. LTD. Full time

Our client’s mission is to develop the lowest-power semiconductor solutions to enable intelligent devices everywhere by developing the lowest-power semiconductor solutions to drive a more energy-efficient, sustainable, and data-driven world. They have helped leading manufacturers worldwide develop products that last weeks on a single charge (rather than days), while delivering a maximum feature set in compact industrial designs. Their goal is to take Artificial Intelligence (AI) where it has never gone before in mobile and portable devices, using their advanced ultra-low power system on chip (SoC) solutions.

The SPOT Low Power Engineer (SLPE) will drive power related activities for their next
- generation products. This will include pre-silicon power modeling, power estimation, post-silicon power correlation and power reduction. The SLPE will work closely with other members of the Advanced Development team and the broader engineering community to develop ultra-low power design methodologies, test them out, and then deploy them in test chips at 12nm and beyond. The SLPE will also work closely with the Engineering team to transition new low power methodologies to support production chip development.
- Work with System, Architecture and Product Planning team to build and own pre
- silicon power modeling, power estimation and post-silicon power correlation. Work closely with the Engineering team to track RTL and gate level power changes during project execution and co-ordinate with design engineers and architects to deploy low power design methods for power reduction.
- Investigate, plan, and test sub-threshold and near-threshold design methodologies and other related low power techniques for power optimization (e.g., customized standard cells, level shifters, retention flops, multi-bit flops etc.
- Validate and refine new low power design techniques as part of a team that is building complex test chips in advanced nodes (e.g., 12nm and beyond). Maintain a relationship and collaborate with 3rd party CAD tool vendors and foundries during the development of new methodologies.

**Requirements**:

- A master’s degree in electrical engineering or a related field is required.
- Experience in pre-silicon power modeling, analysis, and power reduction, withproficiency in PTPX, Power Artist, or other power analysis tools and post-siliconpower correlation
- Strong understanding of Low Power design methodologies, CPF/UPF, goodunderstanding of physical design flow and timing closure with actual implementationexperience as a plus.
- Experience developing new methodologies and transitioning those technologies toproduction is highly desirable.
- Knowledge in system architecture and SOC components such as CPU, fabric andperipherals
- Experience in system and on-die power integrity and EM would be an addedadvantage.
- Proficiency in scripting languages such as Shell, Perl or Python. Possess strongproblem-solving and analytical skills.

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