Packaging Engineer

21 hours ago

Singapore Silicon Labs Careers Full time

-

Meet the Team

Silicon Labs Packaging Organization is dedicated to utilizing, evaluating, and procuring technologies within the industry that allow us to design and create semiconductor packages that advance the growth and market share of our products. The team advances Packaging technology through cutting-edge R&D activities and our strong partnerships with top-tier factories. We aspire to be the best within the industry at package procurement execution and high-performance differentiation.

**Responsibilities**:
You will be based in Singapore, but may be required to travel within the region in the performance of your duties. You will be required to devote total attention and full time to the business and affairs of the Company, its subsidiaries and its affiliated companies as required, discharging the responsibilities assigned to you. Your responsibilities will primarily include but not limited to:
- Confirms Assembly Design Capability and Design for Manufacturing Rules and works with supplier on continuous improvement.- Helps to maintains database for the Package/Process Technology roadmap, Qual reports and Qual data.- Works closely with internal Business Technology team and external suppliers to ensure product designs are optimized.- Conceptualizes cost down activities/projects to support the packaging’s cost target.- Reviews the new processes and technology of the new products with the Manufacturing and Quality teams before going to full production stage.- Works with suppliers on DOE matrix/qualification needed to achieve long term solution & ensure manufacturability of product/process.- Monitors qualification builds in support of supplier PCN, coordinating both reliability and final test.- Conducts regular audit/meetings to resolve issues and set out the improvement action activities at supplier’s site.- Works with material suppliers to determine the feasibility/assessment of potential solutions.

Skills You Will Need
- Minimum Qualifications:_- BSME,EE,ECE or relevant Engineering discipline, in IC package design and assembly manufacturing processes- 1-2 years experience in Semiconductor Assembly Manufacturing environment, knowledge in assembly process and familiarity with various Semiconductor Packages such as WLCSP, QFN, LGA and SiP packages- Good in communication skills orally and in writing- Excellent knowledge of AutoCAD and familiarity with Cadence Allegro SiP/MCM software

Benefits & Perks:

- You can look forward to the following benefits:_- Employee Stock Purchase Plan (ESPP)- Insurance plans with Outpatient cover- Flexible work policy

LI-Hybrid

LI-DK1
- We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status._

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