Asic Dft Engineer

1 week ago

Yishun, Singapore Broadcom Full time

Please Note:
Job Description:
Responsibilities
- Perform ATPG pattern generation including SSA /Transition/RSQ Path Delay and IDDQ pattern using Siemens Tessen tools.
- Perform ATPG verification and simulation playback using Synopsys/ Cadence simulator.
- Strong Analytical mindset and simulation debug capabilities to resolve simulation mis-match.
- Good design knowledge needed that can help improve the test coverage the low coverage of a design.
- Deliver high quality ATE patterns for production ATE testing.
- Provide test pattern support to ATE engineering team for initial prototype bring up and failure analysis in the use of ATPG test and scan/debug features.

Requirements
- Minimum of Bachelor degree or equivalent in Electrical or Computer Engineering.
- Familiar with HDL design language
- Good working knowledge of UNIX/Linux and scripting languages (e.g., TCL, bash, Perl, python)
- Knowledge of ASIC design.
- Strong problem solving skills.
- Team player with strong communication skills.
- 2 - 5 years working experience in a relevant field, e.g. ASIC design, HDL coding

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, gender identity, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

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