RTL Design Engineer

2 hours ago


Singapore Central Singapore Uni Connect Full time $80,000 - $120,000 per year
  • Understanding
    design specification and performing RTL design of the IP using Verilog/System
    Verilog
  • Perform design
    verification, formal verification and code coverage analysis of the IP
  • Understanding
    timing constraints to ensure that the IP passes post-layout simulation
  • Create clear
    and precise documentation for the design
  • Support
    post-silicon validation effort


Requirements
  • Understanding
    design specification and performing RTL design of the IP using Verilog/System
    Verilog
  • Perform design
    verification, formal verification and code coverage analysis of the IP
  • Understanding
    timing constraints and applying right timing constrints
  • Create clear
    and precise documentation for the design
  • Support
    post-silicon validation effort


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