Staff / Senior Engineer, Design Verification (SystemVerilog/UVM)

JOB DESCRIPTION:Responsibility for test plans, testbench documentation and implementation.Use SystemVerilog language, SVA and UVM methodology for block level verification.Debug tests with design engineers to deliver functionally correct design blocks.Close coverage measures to identify verification holes and show progress towards tape-out.Write scripts to...

**Location** Singapore, Central Singapore **Job Type** Full Time **Salary** $5,000 - $9,000 Per Month **Date Posted** 1 hour ago Additional Details **Job ID** 5273 **Job Views** 1 **Job Description**: Roles & Responsibilities - Experience in UVM verification methodology - Experience in developing and deploying state-of-the-art verification...

Key responsibilities:Digital IC Design VerificationPerform front-end verification using UVM methodologyWork with Systems and Software engineers on FPGA verificationLead DFT related activities - Scan Insertion, ATPG, Pattern ValidationWork with test team in debugging production test issuesHelp debug & correct any functional issues found in taped-out...

JOB DESCRIPTIONIn this position, the individual thoroughly understands digital design specs of various IP blocks and SoC architecture definition.Develop detailed module level and SoC level test plans for all the functional features, based on the design spec.Develop ASIC verification environment including all the respective components such as stimulus,...

JOB DESCRIPTIONIn this position, the individual thoroughly understands digital design specs of various IP blocks and SoC architecture definition.Develop detailed module level and SoC level test plans for all the functional features, based on the design spec.Develop ASIC verification environment including all the respective components such as stimulus,...

JOB DESCRIPTIONIn this position, the individual thoroughly understands digital design specs of various IP blocks and SoC architecture definition.Develop detailed module level and SoC level test plans for all the functional features, based on the design spec.Develop ASIC verification environment including all the respective components such as stimulus,...

**Company Overview**: The Staff Physical Design Engineer is responsible for all phases of the physical implementation of complex modules in advanced process technologies from RTL to GDS, emphasizing synthesis, floor-planning, CTS, Place & Route, timing closure, power analysis, power grid analysis, and physical verification. In addition, the Staff Physical...

Data Centre Protocol Engineer / Architect (Multiple Levels)West (8 – 10 Mins Walk from Circle Line MRT)5 days, 9:00 am – 6:00pmBasic Salary up to $6500 (Commensurate with experience) + High Bonuses + Good BenefitsResponsibilities:Design, analyze, and optimize network protocols such as Ethernet, UEC, and UAlink for next-generation data centre...

**Location** Singapore, Central Singapore **Job Type** Full Time **Salary** $6,500 - $12,999 Per Month **Date Posted** 3 minutes ago Additional Details **Job ID** 6870 **Job Views** 1 Roles & Responsibilities Xilinx is now part of Advanced Micro Devices (AMD). At AMD, we push the boundaries of what is possible. We believe in changing the world...

What will you be working on:1.Design one or several of the following high performance analog circuit: high speed and low power ADC, high linearity and low noise amplifier, high linearity and low noise analog filter; high performance PLL, low noise OSC, high speed SERDES, inductive or capacitive base power converter, low noise LDO, high performance...