Staff / Senior Engineer, Design Verification (SystemVerilog/UVM)
7 days ago
Our client is a leading startup in the semiconductor field and a leader in designing ultra low-power microprocessors. The Singapore office houses the Regional Technology Design Center which will be driving the growth and innovation for its products.
R&D – Staff / Senior Engineer – Design Verification
Responsibilities:
- Design and implement UVM-based testbenches and integrate third-party VIPs for SoC-level verification.
- Develop drivers, monitors, and innovative test cases covering power, performance, and functionality.
- Collaborate on gate-level simulations, FPGA bring-up, and automate verification workflows for efficiency.
Requirements:
- Bachelor's/Master's in EE with 5–12 years in SoC/block-level verification and low-power designs.
- Strong in SystemVerilog (UVM), C/C++, scripting (Python/Perl), and AMBA protocols (AXI/AHB/APB).
- Experience with ARM SoCs, mixed-signal designs, and domains like AI edge, video, and audio preferred.
Interested applicants, kindly send in a copy of your updated resume in WORD document to stating your current and expected remuneration together with notice period required to current employer.
You can also contact Vincent Low for a confidential discussion at
EA Personnel Registration No: R1324700
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