Staff Engineer-RTL Design

2 hours ago


Singapore Central Singapore Uni Connect Full time $120,000 - $180,000 per year

Responsibilities

  • Own and be responsible for pre-tape out quality for digital SOC modules on the MCU
  • Explore architecture and develop micro-architecture.
  • RTL development for IPs and SOCs using Verilog
  • 3rd party IP identification, selection, and integration
  • Collaboration with verification and FPGA teams in test plan development and debug
  • Collaborate with the Physical Design team to close the design on timing and power targets
  • Assist in silicon bring-up and validation; 
  • Run tool for quality checks (LINT, CDC, and RDC) and fix/waive the issues


Requirements Requirements
  • Bachelor's degree in Electronics Engineering, Electrical Engineering, Instrumentation & Control Engineering, or a related field, plus 5-8 years of experience.
  • Possess deep and broad knowledge of current and emerging SOC design technologies.
  • Have expert knowledge in designing, implementing, and troubleshooting IPs and SOC
  • Demonstrate a deep understanding of customer needs and the competitive landscape.
  • Ability to estimate the impact of and help plan and lead the implementations and have a positive impact on the entire output
  • Can architect and guide programs across the full range of technical areas.



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