Layout Engineer

7 days ago

Singapore ZERO-ERROR SYSTEMS PTE. LTD. Full time

**Layout Engineer for Silicon IP development**
- Develop digital and analog library cells in various technologies (e.g. CMOS & SOI)
- Layout digital cells for various trade-offs (including speed, power, area, reliability)
- Layout analog circuits and IO circuits
- Characterize digital cell cells for timing and power analyses
- Construct test structures for validating various digital and analog cells
- Analyze the reliability issues (e.g. soft-errors) for various digital cells
- Support the front-end team for System-on-Chip (SoC) integration
- Document the development of digital and analog cells

**Minimum Qualifications**
- Possess at least a Bachelor Degree or equivalent in Electrical & Electronic Engineering or any related field with background on Integrated Circuit Design (both Analog and Digital)
- Knowledge in Electronic Design Automation (EDA) tools (e.g. Cadence, Synopsys, Silvaco)
- Knowledge in cell characterization tools (e.g. Liberate or SiliconSmart or Viola)
- Knowledge in Application Specific Integrated Circuit (ASIC) designs (full custom design methodology)
- Knowledge in digital circuit reliability issues (e.g. latch-up, soft error rates, aging, threshold voltage shift, etc.)
- Experience in digital foundation library cell development (e.g. combinational cells, sequential logic cell, memory cells, IOs)
- Experience in library cell characterization (e.g. understanding in various timing and power models)
- Experience on circuit testing
- Proficiency in English

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