Director, SOC

2 weeks ago

Singapore Ambiq Micro, Inc Full time

Description:
**Company Overview**

**Scope**

As the Job Title at Ambiq, you will drive the **frontend design that includes Microarchitecture, RTL design and Design Verification. In addition, in this role, will interact with customers as needed.**

This role will work with the global SOC team as well as with the Architecture, Software, PostSilicon and customer facing teams.

The person in this role will build front end design capability in Singapore and expand to drive a full SOC design (RTL/DV and other functions). The front end design capability includes microarchitecture, RTL design, Design verification including gate level simulations, IO timing of various interfaces etc.

**Responsibilities**
- Responsible for high quality, on-time tapeouts with good influencing, driving collaboration skills.
- Attract and retain a world class team of RTL and DV engineers. Define team objectives and outcomes; enable success across boundaries; Help the team adapt and learn
- Have keen eye to details across various chip design & implementation functions.
- Budget & Resource management working with functional leads and exec management.
- Keen in establishing processes and automation that ensures quality and enable reliable tapeouts
- Support SOC Design, Physical Design, Design Verification, Post-Si org.
- Track Design Metrics etc and generate relevant data for SoC org for tracking purposes.
- Drive Lesson Learnt for SOC org and drive closure of action items
- Schedule different design reviews (HLDR, MLDR, LLDR etc)
- Goals tracking for team: Tracking and reporting Goals
- Interact and support customers as needed to debug any issues or product presentations

**Requirements**:

- Education Requirements: Minimum requirement for this position is Bachelors in EE or CS.
- Must have overall 15+ year of experience in the Chip Design and Management. Preferably having experience in Microarchitecture, RTL design, DV and Chip Program Management
- Have worked in end to end of SoC design to tapeout experience.
- Should be familiar with Design EDA tools for Synthesis, power (CLP), Constraints Verification.

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