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4 days ago
A global, leading fabless semi-conducter company is hiring a Technical Manager in the area of ASIC/ Design Verification.
- Develop and review test plans.
- Develop verification environment/testbench in Module/IP/SOC level.
- Develop verification IP and reference model.
- Implement test with randomization based coverage driven verification methodology.
- Implement functional and functional/code coverage closure.
- Hands-on code/debug with UVM, System Verilog, Verilog and SystemC.
- Low Power verification.
- Formal verification.
- Verification automation flow.
**Requirements**:
- Bachelor's/Master's Degree in EEE/Computer/IC design /equivalent.
- With min. 10 years (for BSc) / 8 years (for MSc) of relevant verification experiences.
- With IC/ASIC design verification experience on SOC, Ethernet, PCIe, DDR, USB, ARM CPU.
- With strong Experience and debugging ability on SystemVerilog/UVM.
- Skilled in Synopsys/Cadence/Mentor Simulator and debugging flow.
- Experience on Low Power and formal verification is a plus.
- Strong in UNIX scripting with Pyhon, Perl, makefile Cshell.
- Fast learner and a team player.
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