Senior Silicon Design Engineer

Overview:
**WHAT YOU DO AT AMD CHANGES EVERYTHING**

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team.

AMD together we advance_

**Responsibilities**:
**THE ROLE***:
The AMD Serdes team designs high speed serial interface systems which are integrated into various AMD devices.

Layout design is extremely challenging at these smaller process nodes, which needed to consider many un-modelled secondary effects.


**THE PERSON**:
**KEY RESPONSIBILITIES**:

- Full-custom layout design of CMOS high speed and high performance analog mixed signal circuits.
- Cell based layout design (auto place and route) of high speed digital circuits
- Ownership up to entire Gigabits Transceiver (GT) top level or Chip level
- Be able to lead a team to complete a full-scale of layout development task (including scheduling tracking)
- Project Leadership - determine and plan layout schedules and deliverables
- Interface with design engineers, peer layout designers and other internal support groups
- Design should also meeting Process technology-dependent terminologies like device matching, electro-migration, advanced process proximity effects and special techniques like designing latch-up & electro-static discharge immune layouts
- Floor plans complex integration layout with considerations of circuit behaviour and integration requirements
- Verify the correctness and integrity of the layout with respect to design rules, schematics, and integration guidelines.
- Able to run and analyses RC extraction and EM analysis for layout optimization purposes
- Able to do chip floor plan, assemble and verification with digital IP from PNR, foundry IP and analog top level.
- Communication with ESD engineers to implement ESD strategy
- Follow all the necessary prescribed procedures as part of the quality system.
- Collaborate with circuit design team to develop a fully functional silicon product (including project scheduling)
- Perform the above listed duties using advance EDA tools like Cadence Virtuoso Layout XL/GXL suite, Mentor Calibre verification suite & etc.
- Continuous driving methodology development and flow improvement
- Driving layout productivity improvement initiatives (pcell development and automation)
- Other responsibilities include supervision of layout contractors (onsite and offsite), assessing and correcting layout quality issues, and providing feedback to design teams.

**JOB REQUIREMENTS**:

- At least six (6+) years of layout design experience in lower process nodes
- Good understanding of reliability concepts and layout electrical parameters/closure
- Hands-on experience using Cadence and Mentor tools or equivalent
- Strong debug capabilities with parasitic extraction, LVS/DRC, and other physical/electrical verification checks
- Familiarity with circuit design concepts/flows and IC manufacturing processes
- Understanding of parasitic impact on circuit performance and/or digital SoC flow is a plus
- Scripting skills is a plus (Perl, Python, Tcl, etc )
- Ability to work across functions, levels, and remote sites
- Ability to work outside of official working hours, if assigned, to support remote design teams
- Outstanding communication skills and teamwork

**ACADEMIC CREDENTIALS**:

- Bachelor’s in Electrical/Electronics Engineering is required
- Master’s in Electrical/Electronis Engineering is preferred
- Any certification course(s) in VLSI custom layout field will be an added advantage

**LOCATION**:
Singapore

LI-JV1

Qualifications:

- Benefits offered are described: _AMD benefits at a glance
_._