
Senior Digital Verification Engineer
1 week ago
Key Responsibilities
- Develop and Review Test Plans based on IC design specifications to ensure comprehensive coverage.
- Design and implement constrained-Random verification environments for complex digital systems.
- Utilize UVM-SV to develop and modify testbenches and test programs for Pre-Silicon IP/ICs/SOCs, ensuring product performance.
- Implement coverage matrices using cover points and assertions to measure test effectiveness.
- Create and debug tests for digital units (DUTs).
- Collaborate with remote designers to resolve technical issues.
Requirements
- Bachelor's or Master's degree in Electrical/Electronics/Computer Engineering with 1 year of experience or more.
- Hands-on experience with Silicon/IP verification using SystemVerilog/UVM.
- Strong understanding of the verification process from test plan development to coverage completion.
- Effective communication and analytical skills.
- Familiarity with HDL languages (Verilog, VHDL).
- Experience with leading EDA software tools like Cadence/Synopsys.
As a professional in this role, you will have the opportunity to apply your knowledge and skills in a dynamic environment.
Key Skills Include:
- Design Verification
- Analytical Skills
- Synopsys Tools
- Digital IC Design
- Test Cases
- EDA
- UVM
- IP
- SoC
- SystemVerilog
- Semiconductors
- Debugging
- Functional Verification
- Cadence
- ASIC
- Electronic Design Automation (EDA)
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