PMTS - 3D Heterogeneous Integration Engineer (multi-layer stacking for hybrid bonding development)

PMTS - 3D Heterogeneous Integration Engineer (multi-layer stacking for hybrid bonding development)
Join to apply for the
PMTS - 3D Heterogeneous Integration Engineer (multi-layer stacking for hybrid bonding development)
role at
GlobalFoundries
PMTS - 3D Heterogeneous Integration Engineer (multi-layer stacking for hybrid bonding development)
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Join to apply for the
PMTS - 3D Heterogeneous Integration Engineer (multi-layer stacking for hybrid bonding development)
role at
GlobalFoundries
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About GlobalFoundries:
GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world's most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit
Summary Of Role
GlobalFoundries is seeking an experienced 3D Heterogeneous Integration (3DHI) R&D Engineer to drive next-generation multi-layer stacking for hybrid bonding development.
Essential Responsibilities:
Lead 3DHI process development efforts for the building blocks required for advanced packaging solutions needed in the product lines (e.g., multi-die stacking, fine pitch hybrid bonding, etc.) and planning by working with the unit process engineers, manufacturing engineers, as well as directly with the tools & materials for the GF Singapore semiconductor fabs.
Drive end-to-end process integration and planning to enable new capability planning, early product prototyping and qualification across multiple programs.
Develop expertise in the processes, materials and tooling leveraging available characterization resources. Develop integration schemes to continuously improve yields and to reduce cycle time & costs.
Collaborate with vendors and OSATs (Outsourced Assembly and Test) to develop new wafer level and die level 2.5D and 3DHI processes.
Drive understanding of failure modes.
Facilitate advanced packaging interactions between the GF Singapore Product Line/Fab teams and customers.
Generate IP related to novel wafer integration & packaging technology.
Other Responsibilities:
Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs.
Take part in hiring of other Advanced Packaging team members in Singapore.
Mentor and guide new hires to assume their roles and responsibilities.
Other duties as assigned by manager.
Required Qualifications:
Education – Master's in Electrical Engineering, Mechanical Engineering, Chemical Engineering, Materials Science or related field from an accredited degree program.
MS degree with at least 12 years of prior related work experience.
Must have at least an overall 3.0 GPA and proven good academic standing.
Language Fluency - English (Written & Verbal).
Travel - Up to 20%.
Preferred Qualifications:
Education – PhD education level preferred with at least 10 years of prior related work experience.
Demonstrated prior leadership experience in the workplace, school projects, competitions, etc.
Project management skills, i.e. the ability to innovate and execute on solutions that matter; the ability to navigate ambiguity.
Strong written and verbal communication skills.
Strong planning & organizational skills.
Information about our benefits you can find here:
Seniority level
Seniority level Mid-Senior level
Employment type
Employment type Full-time
Job function
Job function Engineering and Information Technology
Industries Appliances, Electrical, and Electronics Manufacturing, IT Services and IT Consulting, and Software Development
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