NPU ASIC IC Design Engineer Entry-Level

**Role and Responsibilities**: - Mixed-Signal IC (MEMS Interface) Design Engineer will be responsible for the design and development of capacitive and/or piezoelectric MEMS interface ASICs, including the required amplifiers, ADCs, filters and control logic, with characteristic high impedance inputs, ultra low power, low noise circuits etc. - The...

**Your new company** Looking for a IC Design engineer role with a listed company that engages in the manufacture and distribution of electrical/ electronics components in Singapore. **Your new role** - The Senior Mixed-Signal IC (MEMS Interface) Design Engineer will be responsible for the design and development of capacitive and/or piezoelectric MEMS...

**Role and Responsibilities**: - Part of the MEMS interface ASIC design team. - Schematic and layout design of mixed-signal circuit to meet specifications. - Plan and execute design activities to meet project schedules. **Requirements**: - Minimum BSEE with hands-on experience in IC Design flow. - Familiarity with modern EDA tools such as Cadence, Mentor,...

Responsibilities Develop design requirements for an NPU based on system-level specifications. Being part of modelling the performance of the NPU module and its data transaction throughput. Microarchitecture design and RTL coding using Verilog / System Verilog HDL for various sub-blocks of the NPU. Understanding the mathematics of different convolution...

About the job (Staff/Sr. Staff) NPU Design Engineer Responsibilities Develop design requirements of an NPU given system level specifications. Being part of modelling the performance of the NPU module and its data transaction throughput. Microarchitecture design and RTL coding using Verilog / System Verilog HDL for various sub-blocks of the NPU. Understanding...

We are seeking a **FPGA/ASIC Engineer **to collaborate with our technical team and take charge of designing and implementing high-performance digital circuits on FPGA or ASIC. Your role will involve managing the entire FPGA build flow, including RTL coding, verification, and timing closure. **Responsibilities** - Design and implement high-performance...

Responsibilities: Develop design requirements for an NPU based on system-level specifications. Being part of modelling the performance of the NPU module and its data transaction throughput. Microarchitecture design and RTL coding using Verilog / System Verilog HDL for various sub-blocks of the NPU. Understanding the mathematics of different convolution...

Responsibilities: Develop design requirements of an NPU given system level specifications. Being part of modelling the performance of the NPU module and its data transaction throughput. Microarchitecture design and RTL coding using Verilog / System Verilog HDL for various sub-blocks of the NPU. Understanding the mathematics of different convolution operators...

In this role you will be part of a world-class IC design team responsible for the development and deployment of software solutions for a revolutionary computing system, which will reduce the energy consumption of AI processing by two orders of magnitude over conventional digital solutions. This will completely disrupt the AI IoT landscape. It is based on our...

Responsibilities: Develop design requirements for an NPU based on system-level specifications. Being part of modelling the performance of the NPU module and its data transaction throughput. Microarchitecture design and RTL coding using Verilog / System Verilog HDL for various sub-blocks of the NPU. Understanding the mathematics of different convolution...