Principal engineer

7 days ago

Singapore Micron Semiconductors Full time

Responsibilities: - Assess Die Overkilling In Line and Optimization of criteria Define Sampling Criteria for Yield Enhancement (YE) Wafer – Initial is to align with RPM lot Define and Create YE In Line DL2 & MRDA Flow: Full scan with tighter criteria (higher magnification) with non-die-kill Create Deviation flow to Route to YE Flow Define and Create YE Probe Flow: Full data logging and Test-to-end to capture as much data as possible Data Analysis: Correlation of MRDA (Metro Real-time defect analysis) Defect to Probe to identify in line failure mode causing probe fail and failure analysis - Manage Risk of deviation - Provide organizational leadership to build functional strategies & processes, and collaborate with partners to deliver strategic solutions Establish organizational roadmaps and strategies. Apply extensive knowledge and tenacity to carry out strategies. Collaborate with peers to construct global solutions. Ensure conflict resolution and assist with identifying escalation paths. Align internal strategies and communicate line of sight to corporate strategic objectives. Establish and communicate department capabilities to ensure partner expectations are aligned. Manage conflict and build effective relationships with internal and external partners. Initiate and sustain effective communication with internal and external partners. Provide advice to senior and executive management on strategic decisions Establishes and manages budget/finances for the team - Ensure a Safe, Compliant, and Ethical Work Environment Maintain knowledge of and apply company safety, labor, and ethics policies. Communicate requirements and expectations to leaders and external partners. Ensure execution of mandatory training for organization. Identify and resolve and / or report potential safety, security, and labor issues. Requirements Bachelors, Masters or Ph D in Electrical Engineering, Materials Science, Chemical Engineering, or related field At least 4 years of experience in Semiconductor Manufacturing and on a leadership capacity, with focus on Advance Packaging technologies and High Bandwidth Memory (HBM) integration, in yield enhancement Experience in PWF (Post Wafer Fabrication), Backend engineering process, assembly package technology development and technical knowledge with die and wafer level process technology with understanding of Micron’s silicon and how it interacts at a package level through CPI (Chip Package Interaction), in yield enhancement Strong leadership and vision and must be able to comfortably work across organizational boundaries and geographies. Demonstrated ability to influence executives, senior leaders and partners on strategic decisions across multiple functions and geographies. Ability to effectively collaborate with multi-functional organizations to understand needs and translate them into actionable plans, deliverables, and resource requirements. Demonstrated ability to drive and implement a wide range of global initiatives with global teams. Ability to be guided by business objectives and determine best methods for delivering results. Organized, meticulous, and strong focus on results. Demonstrated ability to inspire teamwork and to effectively lead others. Proven facilitation skills including the ability to influence others, build consensus, and resolve conflict. Demonstrated track record in baseline performance improvement, business process creation, process simulation techniques, data interpretation skills and proficiency in statistical analysis/method. Excellent analytical skills and organizational competency With good oral and written English communication skill Keen on the role? Apply now #J-18808-Ljbffr

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