Physical Design Engineer
6 days ago
Responsibilities Team IntroductionThe Silicon Platform Team acts as the core R&D middleware group for chip development within the company. The team covers the full spectrum of the chip design flow, including Logic Synthesis, Design for Testability (DFT), Backend Design, Physical and STA (Static Timing Analysis) Signoff, as well as Power Integrity, IR drop, and Electromagnetic Compatibility (Power/IR/EM). The team also oversees tape‑out, mass production, packaging, testing, and board‑level verification. They collaborate closely with front‑end chip teams across business units to drive R&D progress and mass production deployment for chip. 1. Responsible for the block/chip level physical design, from Netlist to GDSII, including Floorplan, Auto Place and Routing, PPA push and signoff work such as Physical Verification / STA / IREM etc. 2. As the foundry contact window, participate in new process introduction, chip tapeout, mass production, packaging and testing, quality control, and other tasks. 3. Participate in project plan evaluation and project initiation preparation. Qualifications Minimum Qualifications1. Bachelor's degree or above, graduated from relevant majors such as microelectronics/computer, with more than 2 years of APR work experience.2. Have proficient scripting skills (e.g., TCL, Perl, Python, etc.).3. Proficiently use mainstream backend tools and master basic backend concepts.4. Have project experience with advanced processes, such as 7nm/5nm/3nm. Preferred Qualifications1. Good teamwork spirit and a serious and responsible work attitude.2. Good communication skills, with fluent English reading and writing abilities. Seniority level Mid‑Senior level Employment type Full‑time Job function Engineering and Information Technology Industries Technology, Information and Internet #J-18808-Ljbffr
-
Physical Chip Design Engineer
1 week ago
Singapore SUNLUNE (SINGAPORE) PTE. LTD. Full time $80,000 - $120,000 per yearJob Overview:We are seeking a motivated and detail-oriented Junior Physical Chip Design Engineer to contribute to the development of low-power, high-performance chip designs. This role will involve learning and assisting in full-chip physical design workflows, including floor planning, place-and-route, power network design, and physical verification, under...
-
Physical Design
2 weeks ago
Singapore UNI CONNECT PTE LTD Full timeResponsibilities: - Fully responsible for Netlist-to-GDS physical design implementation of low power chips **Requirements**: - Bachelor/Masters Degree in Electrical/Computer Engineering - Experience in physical design with tape-outs - Knowledge of complete Netlist-to-GDS flow, Synopsys/Cadence tools like ICC or Encounter - Good in script programming with...
-
Physical Design Engineer
4 days ago
Singapore ALPSOFT TECHNOLOGIES PTE. LTD. Full time**Responsibilities**: - Full responsible for Netlist-to-GDS physical design implementation of 12nm/6nm/4nm and below advanced process chips. - Block owner, take block of 2~3 Million instances, working on Synthesis/APR(auto place and route)/Signoff - Block coordinator role for more than 5~10 blocks, solving the critical issue and give the solution to block...
-
Physical Design Engineer
2 weeks ago
Singapore Voice Way Full time $180,000 - $250,000 per yearJob Description:Lead physical implementation at both block and top levels, including floorplanning, placement, clock tree synthesis (CTS), and routing;Drive timing closure, formal verification, low-power analysis, and power optimization;Perform IR drop and electromigration (EM) analysis, as well as physical verification including DRC, LVS, and ESD...
-
Physical Design Engineer
4 days ago
Singapore BITSILICA PTE. LTD. Full timePhysical Design Engineer Experience: 3+ Years Salary Range: SGD Skills & Technical Expertise Required: Netlist to GDSII at block level, Subsystem Level and at Full chip. Worked on multiple tapeouts on Netlist to GDSII Hierarchical partitioning and budgeting of block-level subsystems. Implementation of high performance (HP) cores, low power designs Node...
-
Staff Physical Design Engineer
3 days ago
Singapore Advanced Micro Devices Full timeWHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our...
-
Physical Chip Design Engineer
4 days ago
Singapore SUNLUNE (SINGAPORE) PTE. LTD. Full timeJob Overview We are seeking a highly skilled and experienced Senior Physical Chip Design Engineer to lead the development and optimization of low-power, high-performance chip design processes. This role requires a deep understanding of advanced semiconductor technologies and the proven ability to oversee full-chip physical design workflows from floor...
-
Physical Design Engineer
5 days ago
Singapore BITSILICA Full timePhysical Design EngineerExperience : 3+ YearsSalary Range :SGD Skills & Technical Expertise Required:Netlist to GDSII at block level, Subsystem Level and at Full chip.Worked on multiple tapeouts on Netlist to GDSIIHierarchical partitioning and budgeting of block-level subsystems.Implementation of high performance (HP) cores, low power designsNode experience...
-
Senior Engineer, Physical Design
3 days ago
Singapore Marvell Technology Full time $120,000 - $240,000 per yearAbout MarvellMarvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries,...
-
Physical Design Engineer
6 days ago
Singapore ByteDance Full timeResponsibilities Team Introduction The Silicon Platform Team acts as the core R&D middleware group for chip development within the company. The team covers the full spectrum of the chip design flow, including Logic Synthesis, Design for Testability (DFT), Backend Design, Physical and STA (Static Timing Analysis) Signoff, as well as Power Integrity, IR drop,...