Digital IC Designer with Power Optimization Expertise
5 days ago
We are seeking an experienced Digital IC Design Engineer to join our team at REALTEK SINGAPORE PRIVATE LIMITED. The successful candidate will be responsible for collaborating with system engineers to refine timing requirements and provide feedback on optimization.
Key Responsibilities:- Timing Closure: Optimization of SoC timing constraint and synthesis for efficient timing closure.
- Power Structure Development: Development and implementation of power structures, including isolation of power domains and level-shifter crossing voltage domains.
- Formal Verification: Conducting formal verification for release comparison purposes.
- Timing Violation Analysis: Support in back-end implementation of timing violation analysis and resolution.
- Scan Insertion and Optimization: Assistance in scan insertion and optimization.
- Power Optimization Initiatives: Collaboration on power structure and power optimization initiatives.
- Bachelor's or Master's degree in Electronic Engineering with experience in ASIC design.
- Familiarity with the ASIC design flow.
- Experience in logic synthesis, static timing analysis, and timing closure.
- Strong understanding of Design-for-Testability (DFT) and power structure concepts.
- Familiarity with UNIX/Linux environment and scripting capabilities.
- Excellent communication and interpersonal skills.
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