Hardware Development Expert

2 weeks ago

Singapore Nanyang Technological University Full time

The School of Electrical and Electronic Engineering at Nanyang Technological University is a world-renowned institution for its high academic standards and research. With over 3,000 undergraduate students and 1,000 graduate students, it is one of the largest EEE schools in the world.

We are seeking a highly skilled Research Associate with experience in RISC-V architecture to join our team. The successful candidate will be responsible for adding a Hardware AES and ASCON Accelerator to the RISC-V CVA6 core.

Key Responsibilities:
  • Integrate a Hardware AES Accelerator and ASCON Lightweight Cryptography Accelerator into the RISC-V CVA6 (Ariane) core.
  • Implement memory-mapped interfaces or custom instructions for the accelerators to interface with the CVA6 core.
  • Collaborate on the integration of the accelerators into the core's execution pipeline.
RISC-V ISA Extension:
  • Define and implement custom RISC-V instructions to utilize the AES and ASCON hardware accelerators, if needed.
  • Modify the RISC-V CVA6 decode and execution stages to handle the new cryptographic instructions.
  • Work out the toolchain to ensure assembler, compiler, and simulation support for the custom instructions.
Verification and Testing:
  • Conduct simulations to evaluate the performance, latency, and throughput of the accelerators within the CVA6 pipeline.
  • Work closely with the AES and ASCON accelerator design team to ensure proper testing and debugging of the hardware integration.

The ideal candidate will have a Master's degree in Electrical Engineering, Computer Engineering, or a related field, and proven experience with RISC-V architecture, especially with custom instruction extensions and pipeline modifications.

Proficiency in HDL languages (Verilog, VHDL, or SystemVerilog) and RTL design is required. Experience in FPGA development tools such as Vivado, Quartus, or similar for prototyping is also essential.

Required Skills and Qualifications:

  • Master's degree in Electrical Engineering, Computer Engineering, or a related field.
  • Proven experience with RISC-V architecture, especially with custom instruction extensions and pipeline modifications.
  • Proficiency in HDL languages (Verilog, VHDL, or SystemVerilog) and RTL design.
  • Experience in FPGA development tools such as Vivado, Quartus, or similar for prototyping.

Preferred Additional Skills:

  • Strong understanding of ASIC/FPGA design flows, including synthesis, place and route, and timing closure.
  • Experience in cryptography and implementing cryptographic algorithms in hardware (AES, ASCON, etc.).

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