Principal Verification Engineer
7 days ago
As a Principal Verification Engineer at UNI CONNECT PTE LTD, you will be responsible for developing detailed module level and SoC level test plans for all functional features based on the design specification. You will also develop ASIC verification environments, including stimulus, checkers, assertions, monitors, and scoreboards.
Key Responsibilities:
- Develop directed and constrain-random verification functional tests and simulate using EDA tools to verify functional specifications are working.
- Execute verification plans, including design bring-up, DV bring-up, regression enabling for all features.
- Collaborate with digital design teams to debug functional test cases and deliver functionally correct designs.
Requirements:
- Bachelor's degree with 5-8 years of relevant industry experience.
- Strong VLSI functional verification experience, preferably with exposure to complex high-speed custom VLSI products.
- Proficiency in hardware functional verification languages and Object-Oriented language development skills, preferably with SystemVerilog/UVM experience.
- Familiarity with ASIC verification methodologies, tools, and development flows.
- Working experience or familiarity with Ethernet L2/L3 switch/router, SOC, AMBA bus, high-speed IO (USB-2/3, PCIe gen2/3, SATA), Flash controller, or CPU peripherals.
Compensation and Benefits:
We offer an estimated salary of SGD 120,000 per annum, commensurate with experience. In addition, we provide a comprehensive benefits package, including health insurance, retirement plan, and paid time off.
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