Senior Digital Chip Verification Engineer with Expertise in Formal Methods
1 day ago
We are seeking a highly skilled Digital IC Verification Engineer to join our team at ESPRESSIF SYSTEMS (SINGAPORE) PTE. LTD.
About the Role:
- Develop verification plans based on design-related documentation and set up the verification environment for chip designs from multiple dimensions.
- Execute regression testing and enhance verification coverage using Verilog and C/SystemVerilog.
- Collaborate with chip design engineers to identify and resolve design defects, ensuring the integrity and correctness of chip designs.
- Guide the design team in implementing a verification-friendly design flow, leveraging expertise in UVM (Universal Verification Methodology).
- Perform RTL-level, gate-level, and low-power verification with UPF (Unified Power Format) and assist FPGA engineers and software engineers in completing FPGA prototype testing.
Requirements:
- Bachelor's degree or higher in Computer Science, Electrical Engineering, Communications Engineering, or related fields, with 3+ years of work experience.
- Experience in design or verification of peripheral modules, communication modules, or SoC systems, with proficiency in Verilog and expertise in C/SystemVerilog.
- Knowledge of one or more scripting languages such as Python, Ruby, Perl, Shell, Tcl, or Makefile, with experience with formal verification being a plus.
- Familiarity with the digital chip development process and successful tape-out project experience is an advantage.
Compensation Package:
The estimated annual salary for this position is $120,000 - $180,000, depending on qualifications and experience.
Benefits:
- Competitive compensation package.
- Ongoing training and professional development opportunities.
- A collaborative and dynamic work environment.
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