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2 weeks ago
As a seasoned technical leader, you will spearhead the design and optimization of complex analog and mixed-signal circuits for next-generation AI chips.
- Key Responsibilities:
- Architect innovative solutions to drive digital standard cell library excellence and guide the development of high-performance libraries.
- Provide strategic direction to layout teams and ensure successful tape-outs through rigorous simulation, analysis, and optimization.
- Lead cross-functional teams and mentor junior engineers in advanced analog design techniques, power optimization strategies, and thorough noise analysis.
- Effectively communicate complex technical concepts to diverse audiences and collaborate seamlessly with digital design, architecture, and verification teams.
- Drive the complete lifecycle of digital standard cell library creation, characterization, and optimization for power, performance, and area.
Requirements:
- Education: Bachelor's degree in Electronics Engineering or related field; Master's or Ph.D. preferred.
- Experience: Minimum 8-12+ years of progressive experience in analog circuit design and digital standard cell development.
- Technical Mastery: Deep expertise in advanced analog design techniques, power optimization strategies, and thorough noise analysis.
- Tool Proficiency: Industry-standard EDA tools such as Cadence Virtuoso, Spectre, and HSPICE.
- Leadership & Communication: Proven ability to lead and inspire technical teams, mentor engineers, and possess exceptional written and verbal communication skills.
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