Principal Engineer/MTS

1 week ago


Singapur, Singapore MICRON SEMICONDUCTOR ASIA OPERATIONS PTE. LTD. Full time
Job Title: Principal Engineer/MTS

At Micron Semiconductor Asia Operations PTE. LTD., we are seeking a highly skilled Principal Engineer/MTS to join our team. As a key member of our NAND development team, you will be responsible for driving innovation and excellence in our memory technology products.

Key Responsibilities:
  • Develop and implement new DFT solutions to reduce DPM, test time, yield hit, and cycle time for qualification.
  • Partner with Design Engineering team to develop and innovate test modes.
  • Own test mode definition to ensure all testing requirements are fulfilled.
  • Drive test mode validation process in pre-silicon and post-silicon phases in collaboration with other PE teams.
  • Respond to silicon DFT-related issues, driving silicon debug and experiments to find practical solutions.
  • Enable best-in-class production testing capabilities and test time efficiencies for cost reductions.
  • Lead efforts to reduce die size.
  • Enable faster development of production DIDs by providing learnings from spider chips.
  • Engage with System teams on innovation and solutions for defect management, improving yield and cycle time for qualification.
  • Lead staging and strategy on future nodes to achieve best-in-class Design and System solutions to improve yield, quality, and test time.
  • Analyze high-volume data to inform decision-making.
  • Mentor and support team members with technical expertise and direction.
Requirements:
  • Bachelor's, Master's, or PhD in Electrical and Electronics Engineering with 15+ years of experience.
  • Strong knowledge of CMOS technology and NAND/DRAM development.
  • Proficient in tackling challenges, leveraging extensive experience in design rule, process, and product qualifications in logic or memory (NAND/DRAM/SRAM).
  • Proficient in ASIC design flow: RTL design, verification, logic synthesis, and timing analysis.
  • Familiar with DFT flow and verification.
  • Experience with digital and analog simulation tools (e.g., Finesim, Hspice, Hsim, Verilog).
  • Experience with System Verilog testbench/UVM/Constrained Random verification.
  • Skilled in RTL development for logic or mixed-signal circuits.
  • Experience in leading and mentoring engineering teams.


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