Design Engineer

4 weeks ago


Singapore EXASOFT PTE. LTD. Full time
Roles & Responsibilities

Responsibilities:

  • Take mixed-signal subsystem design from design implementation to final delivery for chip-level integration
  • Perform micro-architectural studies to determine optimal hardware implementations of IP digital blocks to meet product requirements
  • Ensure all required documentation are prepared according to the quality standards
  • RTL logic design of modules using Verilog HDL. Designs may include power and clock management units, IP subsystem, high speed design, digital interfaces to analog functions, accelerators, filters, etc
  • Prepare and hold design and verification reviews with technical staff throughout project lifecycle
  • Perform logic synthesis, timing and power analysis to optimize designs
  • Pre-silicon verification utilizing various methodologies such as constrained random verification with block/subsystem/chip level UVM test benches, spice co-simulation of mixed signal blocks and FPGA emulation.

Requirements:

  • Engineering Degree in relevant field
  • Related experience in RTL design
  • VLSI Design, RTL programming, Synthesis, power analysis.
Tell employers what skills you have

Hardware
Analog
Mixed Signal
UVM
RTL Design
IP
FPGA
FPGA firmware
Verilog
VLSI

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