DFT Engineer

Roles & Responsibilities

Headquarter in Singapore, WATT AI PTE LTD (www.wattai.tech) is an innovative high-tech company co-founded by hardware and software experts working on next-gen AI processors (ASICs) and models and GPU cloud from Silicon Valley. It is committed to developing high-performance AI chips and computing clusters that support ultra-large-scale AI model training. Create a complete software and hardware integration solution, provide global customers with AI innovation technology solutions with capabilities to produce and evolve, and accelerate the process of AI implementation and industrialization. We are looking to grow our team with the most intelligent people of the world. Together, we can really make a change: IC Architects (3-4 full-time headcounts) directly reporting to co-founder & CTO As a DFT Engineer, your role is about embedding testability features directly into the design phase of these intricate circuits, thereby facilitating streamlined testing procedures, early fault detection, and expedited fault diagnosis during manufacturing. By incorporating DFT principles, engineers significantly mitigate risks associated with defects, accelerate time-to-market, and uphold stringent quality standards, thus fortifying the foundation upon which the semiconductor industry continues to innovate and thrive. Responsibilities 1. Test Structure Integration: DFT engineers work on integrating specific test structures and logic directly into the chip's architecture. This integration involves strategically placing components within the design that allow for comprehensive testing. They create and embed features such as scan chains, Built-In Self-Test (BIST) modules, and other test access mechanisms that enable thorough testing of the chip's functionality. 2. Test Methodologies Development: These engineers are responsible for developing innovative and efficient test methodologies. They design algorithms and strategies aimed at detecting potential faults or defects within semiconductor devices. This involves creating complex testing scenarios and protocols to thoroughly evaluate different functionalities and potential failure points of the chip. 3. Compliance with Standards: DFT engineers ensure that the testability features implemented in semiconductor designs comply with industry standards and protocols. They stay updated with the latest standards and guidelines to ensure compatibility across diverse manufacturing and testing platforms. By adhering to these standards, they enable easier interoperability and compatibility between different chips and testing equipment. 4. Collaboration with Design Teams: DFT engineers collaborate closely with various teams, including design, verification, and manufacturing, to ensure that the testability features are seamlessly integrated into the chip design without compromising its performance or functionality. Their work significantly contributes to the overall quality, reliability, and manufacturability of semiconductor products in the market. 5. Debugging and Troubleshooting: In the event of test failures or issues during manufacturing, DFT engineers troubleshoot problems, analyze test results, and identify the root causes of failures. They work on solutions to rectify these issues and ensure the integrity of the circuits. Key Qualifications 1. A Master's Degree in EE, CS, Math, Physics or related subjects, PhD preferred. 2. Proficiency in digital design and verification methodologies, demonstrates an adept command of digital design principles, navigating the intricacies of RTL coding and simulation. 3. In-depth knowledge of DFT architectures and methodologies, including scan, Built-In Self-Test (BIST), and the intricate intricacies of Design for Debug (DFD). 4. Familiarity with Automatic Test Pattern Generation (ATPG) tools and fault models to generate efficient test patterns for manufacturing tests. Preferred Qualifications 1. Expertise in scripting languages (e.g., Perl, Python). 2. Strong understanding of industry-standard test protocols and standards (e.g., IEEE 1149.1, IEEE 1500).

Job scope

As a DFT Engineer, your role is about embedding testability features directly into the design phase of these intricate circuits, thereby facilitating streamlined testing procedures, early fault detection, and expedited fault diagnosis during manufacturing. By incorporating DFT principles, engineers significantly mitigate risks associated with defects, accelerate time-to-market, and uphold stringent quality standards, thus fortifying the foundation upon which the semiconductor industry continues to innovate and thrive.

Responsibilities

1.

Test Structure Integration: DFT engineers work on integrating specific test structures and logic directly into the chip's architecture. This integration involves strategically placing components within the design that allow for comprehensive testing. They create and embed features such as scan chains, Built-In Self-Test (BIST) modules, and other test access mechanisms that enable thorough testing of the chip's functionality.

2.

Test Methodologies Development: These engineers are responsible for developing innovative and efficient test methodologies. They design algorithms and strategies aimed at detecting potential faults or defects within semiconductor devices. This involves creating complex testing scenarios and protocols to thoroughly evaluate different functionalities and potential failure points of the chip.

3.

Compliance with Standards: DFT engineers ensure that the testability features implemented in semiconductor designs comply with industry standards and protocols. They stay updated with the latest standards and guidelines to ensure compatibility across diverse manufacturing and testing platforms. By adhering to these standards, they enable easier interoperability and compatibility between different chips and testing equipment.

4.

Collaboration with Design Teams: DFT engineers collaborate closely with various teams, including design, verification, and manufacturing, to ensure that the testability features are seamlessly integrated into the chip design without compromising its performance or functionality. Their work significantly contributes to the overall quality, reliability, and manufacturability of semiconductor products in the market.

5.

Debugging and Troubleshooting: In the event of test failures or issues during manufacturing, DFT engineers troubleshoot problems, analyze test results, and identify the root causes of failures. They work on solutions to rectify these issues and ensure the integrity of the circuits.

Key Qualifications

1.

A Master's Degree in EE, CS, Math, Physics or related subjects, PhD preferred.

2.

Proficiency in digital design and verification methodologies, demonstrates an adept command of digital design principles, navigating the intricacies of RTL coding and simulation.

3.

In-depth knowledge of DFT architectures and methodologies, including scan, Built-In Self-Test (BIST), and the intricate intricacies of Design for Debug (DFD).

4.

Familiarity with Automatic Test Pattern Generation (ATPG) tools and fault models to generate efficient test patterns for manufacturing tests.

Preferred Qualifications

1.

Expertise in scripting languages (e.g., Perl, Python).

2.

Strong understanding of industry-standard test protocols and standards (e.g., IEEE 1149.1, IEEE 1500).

Tell employers what skills you have

Perl
Static Timing Analysis
Semiconductor Industry
Industrialization
Physics
Scripting
Product Engineering
Technology Solutions
SoC
Test Methodologies
DFT
Test Development
Debugging
IC
Atpg
Silicon

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