SOC Physical Design Engineer

Roles & ResponsibilitiesResponsibility Responsible for high-performance block implementation (RTL to GDSII). Perform block level floor planning, power grid implementation, APR placement, timing optimization, CTS and routing. Close the design to meet timing, power budget and area targets. Run physical verification flows (DRC/LVS/EM/IR), and implement...

Roles & ResponsibilitiesResponsibility Responsible for high-performance block implementation (RTL to GDSII). Perform block level floor planning, power grid implementation, APR placement, timing optimization, CTS and routing. Close the design to meet timing, power budget and area targets. Run physical verification flows (DRC/LVS/EM/IR), and implement...

Roles & ResponsibilitiesResponsibilityResponsible for high-performance block implementation (RTL to GDSII). Perform block level floor planning, power grid implementation, APR placement, timing optimization, CTS and routing. Close the design to meet timing, power budget and area targets. Run physical verification flows (DRC/LVS/EM/IR), and implement fixes...

Roles & ResponsibilitiesJob Description: Responsible for physical design, development for variety of SoC(System On Chip) and tapeout. Execute state-of-art methodologies include, floor-planning, place and route, RC extraction, timing and power optimization, physical verification. Doing benchmarking on Performance/Power/Area to validate the robustness of...

Roles & ResponsibilitiesJob Description: Responsible for physical design, development for variety of SoC(System On Chip) and tapeout. Execute state-of-art methodologies include, floor-planning, place and route, RC extraction, timing and power optimization, physical verification. Doing benchmarking on Performance/Power/Area to validate the robustness of...

Roles & ResponsibilitiesKey ResponsibilitiesResponsible for delivering system-on-chip (SoC) Full-Chip Static Timing Analysis. Define and own full chip timing constraint, timing signoff criteria, perform full chip STA, timing ECO creation and oversee final timing signoff for SoCs, and managing tape-outs day-to-day driven by development team. Be responsible...

JOB DESCRIPTION Discussion with system engineers on SoC architecture and feedback on optimization. Work on SoC integration; system block development, e.g., power management, clock/reset, system register, test control, PinMux, etc; Discussion with synthesis engineer and back-end engineer on design optimization.    SoC DFT support; SoC verification plan and...

JOB DESCRIPTION In this position, the individual thoroughly understands digital design specs of various IP blocks and SoC architecture definition. Develop detailed module level and SoC level test plans for all the functional features, based on the design spec. Develop ASIC verification environment including all the respective components such as stimulus,...

JOBDESCRIPTION Discussion with system engineers on SoC architecture andfeedback on optimization. Work on SoCintegration; system block development, e.g., power management,clock/reset, system register, test control, PinMux, etc;Discussion with synthesis engineer and back-end engineeron design optimization.    SoC DFTsupport; SoC verification plan and...

Roles & ResponsibilitiesKey Responsibilities Responsible for delivering system-on-chip (SoC) Full-Chip Static Timing Analysis. Define and own full chip timing constraint, timing signoff criteria, perform full chip STA, timing ECO creation and oversee final timing signoff for SoCs, and managing tape-outs day-to-day driven by development team. Be...

JOB DESCRIPTION Understand the product requirement and create SOC system level architecture according to the requirement.  Understand the use case and create system level test plan. Define design specification for new hardware modules, together with IC design engineer. Work with IC design engineers to resolve the issues during design phase and qualify the...

JOB DESCRIPTION Work with SoC Integration and SoC Timing on power structure optimization Work on UPF development to support different stages of implementation flow and SoC verification Work on power structure, eg. Isolation of power domains, level-shifter crossing voltage domains Conduct power structure check at different implementation stages.  Support...

Roles & ResponsibilitiesJob Description:We are seeking a SoC Verification Engineer to test and validate System-on-Chip (SoC) designs. You will work with cross-functional teams to ensure chip functionality through verification using UVM, SystemVerilog, Python, and other cutting-edge tools.Responsibilities:Develop verification plans for module and system-level...

Roles & ResponsibilitiesPosition Overview:We are seeking a skilled Physical Design Engineer to join our team. As a Physical Design Engineer, you will be responsible for the entire process from RTL to GDS, ensuring the successful implementation of complex semiconductor chips. You will focus on block-level timing closure, formal checks, low power checks, power...

Roles & ResponsibilitiesResponsibilities: Work closely with design engineers and architects to create and document detailed test plans for verifying the SoC design. Establish and manage the infrastructure and environment for automated verification of the SoC's architecture, functionality, and performance. Develop reusable testbenches, test cases using...

Roles & ResponsibilitiesJob role:1. Works with the front-end design team to complete the chip floorplan , clockarchitecture, and powerplan .2. Takes charge of the physical design tasks from the Netlist to the GDS2, including P&R, formal verification, static timing analysis, physical verification, power analysis, design for reliability (DFR) and tapeout.3....

Roles & ResponsibilitiesJob Responsibilities Participate in feature definitions of the leading-edge AI chips. Participate in the microarchitecture design of AI chip SoC and the subsystems. Participate in the front-end design and the implementation using HDLs. Perform critical analysis and propose novel chip architectures for performance, power, and area...

Roles & ResponsibilitiesJob Responsibilities Participate in feature definitions of the leading-edge AI chips. Participate in the microarchitecture design of AI chip SoC and the subsystems. Participate in the front-end design and the implementation using HDLs. Perform critical analysis and propose novel chip architectures for performance, power, and area...

JOBDESCRIPTION In this position, theindividual thoroughly understands digital design specs of variousIP blocks and SoC architecture definition. Develop detailed module level and SoC level test plansfor all the functional features, based on the designspec. Develop ASIC verification environmentincluding all the respective components such as stimulus,...

JOBDESCRIPTION In this position, theindividual thoroughly understands digital design specs of variousIP blocks and SoC architecture definition. Develop detailed module level and SoC level test plansfor all the functional features, based on the designspec. Develop ASIC verification environmentincluding all the respective components such as stimulus,...