Senior Physical Design Engineer

3 months ago

Singapur, Singapore MANPOWER STAFFING SERVICES (SINGAPORE) PTE LTD Full time
Roles & Responsibilities

Position Overview:


We are seeking a skilled Senior Physical Design Engineer to join our team. As a Senior Physical Design Engineer, you will be responsible for the entire process from RTL to GDS, ensuring the successful implementation of complex semiconductor chips. You will focus on block-level timing closure, formal checks, low power checks, power analysis, and signoff for block-level physical implementation. Your expertise in advanced process nodes, low-power design, and automotive chip physical design will contribute to the development of cutting-edge semiconductor products.


Responsibilities:

  • Lead the physical design process, overseeing RTL to GDS implementation for semiconductor chips.
  • Achieve block-level timing closure by optimizing design constraints, performing timing analysis, and applying optimization techniques.
  • Conduct formal checks to ensure designs meet functional and timing requirements.
  • Perform low-power checks and analyze power consumption to optimize power efficiency.
  • Collaborate with the design team to develop and implement UPF (Unified Power Format) for power management and control.
  • Execute block-level Place and Route (APR), Static Timing Analysis (STA), Power Integrity (PI), Physical Verification (PV), and Formal Verification (FM) signoff processes.
  • Utilize Synopsys and Cadence APR (Automated Routing and Place) tools for high-quality physical design.
  • Develop and employ scripts in Tcl, Perl, or Python to automate design tasks and improve the design flow.
  • Mentor junior engineers and provide technical guidance and support as needed.

Qualification/ Requirements:

  • Bachelor's/master’s degree in electrical engineering, Computer Engineering, or a related field.
  • 3-5 years of experience in physical design for semiconductor chips.
  • Proficiency in RTL-to-GDS flow, timing closure, low-power design, and power analysis.
  • Strong understanding of UPF for power management and control.
  • Experience with block-level Place and Route (APR), Static Timing Analysis (STA), Power Integrity (PI), Physical Verification (PV), and Formal Verification (FM) signoff.
  • Familiarity with Synopsys and Cadence APR/Sign-off tools.
  • Proficiency in scripting languages such as Tcl, Perl, or Python for automation.
  • Able to guide junior colleague when needed.
  • Excellent problem-solving skills and ability to work effectively in a team environment.

Tell employers what skills you have

Perl
Static Timing Analysis
Timing Closure
Floorplanning
Scripting
Routing
EDA
Power Management
Python
Cadence
Budgeting
IC
Physical Design
Electrical Engineering

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