Senior Verification Engineer
4 weeks ago
Job Responsibilities:
- Develop module level and system level verification plans based on design spec;
- Build verification environment using UVM infrastructure ;
- Define reasonable functional coverage according to the verification plan, add test vectors, and meet the requirements for functional coverage and code coverage;
- Complete the verification tasks of each stage of the chip, meet the verification requirement of each node, and successfully stream the chip;
- Complete the verification report of the responsible module and pass the verification review.
Job Requirements
- Master's degree or above, major in microelectronics, electronic engineering, integrated circuit, etc;
- Deep understanding on ASIC design and verification flow;
- Excellent knowledge of verification methodology like system Verilog, UVM;
- Ability to analyze and solve problems independently;
- Master at least one script development language: python/perl/tcl/shell;
- Experience in chip verification for specific projects is preferred, while experience in UVM verification is preferred.
Tell employers what skills you have
Hardware
Documentation Skills
Electrical
Test Cases
EDA
UVM
IP
SoC
SystemVerilog
Ethernet
Flash
Functional Verification
ASIC
Debugging
Verilog
VLSI
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